A porous Ge/Si interface layer for defect-free III-V multi-junction solar cells on silicon

Bioud, Youcef A.; Beattie, Meghan N.; Boucherif, Abderraouf; Jellit, Mourad; Stricher, Romain; Ecoffey, Serge; Patriarche, G.; Tománek, David; Soltani, A.; Braidy, Nadi; Wilkins, Matthew M.; Valdivia, Christopher E.; Hinzer, Karin; Drouin, Dominique; Arès, Richard

doi:10.1117/12.2511080

Cited by 9 publications

(3 citation statements)

References 21 publications

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“…A wide range of approaches is being considered, which either lift-off thin Ge foils from a Ge wafer or avoid using Ge at all by lifting-off III-V foils from gallium arsenide (GaAs) wafers, or by growing on alternative substrates such as silicon (Si). The III-V layer quality on silicon wafers or virtual Ge substrates [2][3][4][5] is far from being on par with GaAs and Ge. If in the future, progress could be expected from remote epitaxy, 6 the currently most advanced approaches are the epitaxial lift-off (ELO) technique, spalling and release from porous germanium.…”

Section: Introductionmentioning

confidence: 99%

Wafer‐scale Ge epitaxial foils grown at high growth rates and released from porous substrates for triple‐junction solar cells

Depauw

Porret

Moelants

et al. 2022

Progress in Photovoltaics

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Germanium is listed as a critical raw material, and for environmental and economic sustainability reasons, strategies for lower consumption must be implemented. A promising approach is Ge lift‐off concepts, which enable to re‐use the substrate multiple times. Our concept is based on the Ge‐on‐Nothing approach that is the controlled restructuring at high temperature of a macroporous Ge surface, forming a Ge foil weakly attached to its parent wafer. Its suitability as III–V epitaxy seed and support substrate has previously been demonstrated with proof‐of‐concept solar cells. This work focuses on bringing this concept to the next level, by upscaling the detachable area to a full 200‐mm wafer scale, increasing foil thickness for sufficient light absorption in the Ge bottom cell, and improving the control on the strength that is bonding the suspended foil to its parent. By introducing a new high growth‐rate epitaxy process from GeCl4, and by engineering the GeON structure to introduce pillars with ad hoc density and shape, we fabricated P‐type foils with tunable boron doping up to 15 μm in thickness and 11 cm × 11 cm in area, for which the detachment strength could be adapted to the stresses induced by the solar cell process steps. The surface roughness and the electrical and crystal qualities of these foils were inspected by AFM, SIMS, SRP, ECCI, and TEM to check the GeCl4‐based epitaxy conditions and to check that the ad hoc pillars were not introducing any damage. Small‐area triple‐junction lattice‐matched GaInP/GaInAs/Ge solar cells were fabricated on 7‐μm‐thick Ge foils with various pillar densities and on a standard reference Ge wafer. The III–V layer nucleation was virtually the same on both substrates and the solar cells on the GeON foils performed in the same way as the cells on the Ge wafer, albeit a small loss in short‐circuit current and open‐circuit voltage that can be attributed to the thickness reduction and absence of rear‐side passivation. We conclude that it is possible to gain control on the GeON detachability and upscale the concept to areas relevant for the space PV industry, proving that porous germanium is a serious candidate for replacement of bulk Ge wafers in view of a more sustainable multijunction solar cell process.

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Section: Introductionmentioning

confidence: 99%

Wafer‐scale Ge epitaxial foils grown at high growth rates and released from porous substrates for triple‐junction solar cells

Depauw

Porret

Moelants

et al. 2022

Progress in Photovoltaics

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“…High magnification scanning transmission electron microscopy (STEM) view reveals the dislocation-void interaction, and shows that threading dislocations are looping at the void (Fig 1 .b). Our observations show that this architecture referred to as nanovoid-based Ge/Si virtual substrate (NVS) is effective in reducing the TD density [12][13][14][15][16][17][18] . To quantify the reduction in TD density with lower magnification images, etch-pit density (EPD) analyses were carried out.…”

Section: Resultsmentioning

confidence: 99%

Capturing the Effects of Free Surfaces on Threading Dislocation Density Reduction

Bioud¹,

Boucherif²,

Patriarche³

et al. 2020

ECS Trans.

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The big concern with using silicon as a substrate for making Ge and III-V devices is the dislocation density in the epilayers. Dislocations degrade device performance by trapping the photo-generated carriers, dragging down efficiency. In this manuscript, a Ge/Si substrate is treated with a post epitaxial process to create a region with a high density of nanovoids within the Ge/Si structure, which acts as a free surface that attracts dislocations, facilitating the subsequent annihilation of their threading arms. Nanovoids are formed in the Ge layer by electrochemical porosification, followed by thermal annealing, creating a new configuration referred to as nanovoid-based Ge/Si virtual substrate (NVS).

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“…However, the Ge film in the NVS is almost fully relaxed, the strain relaxation is engineered elastically thanks to the voided Si substrate. Due to its porosity, the elastic modulus of Si is reduced and the substrate can be stretched, compressed, and deformed 74–76 . It is therefore expected to accommodate the mismatch of heterogeneous layers and to serve as a mechanically stretchable compliant substrate.…”

Section: Resultsmentioning

confidence: 99%

Uprooting defects to enable high-performance III–V optoelectronic devices on silicon

Bioud¹,

Boucherif²,

Myronov³

et al. 2019

Nat Commun

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The monolithic integration of III-V compound semiconductor devices with silicon presents physical and technological challenges, linked to the creation of defects during the deposition process. Herein, a new defect elimination strategy in highly mismatched heteroepitaxy is demonstrated to achieve a ultra-low dislocation density, epi-ready Ge/Si virtual substrate on a wafer scale, using a highly scalable process. Dislocations are eliminated from the epilayer through dislocation-selective electrochemical deep etching followed by thermal annealing, which creates nanovoids that attract dislocations, facilitating their subsequent annihilation. The averaged dislocation density is reduced by over three orders of magnitude, from ~108 cm−2 to a lower-limit of ~104 cm−2 for 1.5 µm thick Ge layer. The optical properties indicate a strong enhancement of luminescence efficiency in GaAs grown on this virtual substrate. Collectively, this work demonstrates the promise for transfer of this technology to industrial-scale production of integrated photonic and optoelectronic devices on Si platforms in a cost-effective way.

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A porous Ge/Si interface layer for defect-free III-V multi-junction solar cells on silicon

Cited by 9 publications

References 21 publications

Wafer‐scale Ge epitaxial foils grown at high growth rates and released from porous substrates for triple‐junction solar cells

Wafer‐scale Ge epitaxial foils grown at high growth rates and released from porous substrates for triple‐junction solar cells

Capturing the Effects of Free Surfaces on Threading Dislocation Density Reduction

Uprooting defects to enable high-performance III–V optoelectronic devices on silicon

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