Capturing the Effects of Free Surfaces on Threading Dislocation Density Reduction

Abstract

The big concern with using silicon as a substrate for making Ge and III-V devices is the dislocation density in the epilayers. Dislocations degrade device performance by trapping the photo-generated carriers, dragging down efficiency. In this manuscript, a Ge/Si substrate is treated with a post epitaxial process to create a region with a high density of nanovoids within the Ge/Si structure, which acts as a free surface that attracts dislocations, facilitating the subsequent annihilation of their threading arms. Nanovoids are formed in the Ge layer by electrochemical porosification, followed by thermal annealing, creating a new configuration referred to as nanovoid-based Ge/Si virtual substrate (NVS).

Dual-Step Selective Homoepitaxy of Ge with Low Defect Density and Modulated Strain Based on Optimized Ge/Si Virtual Substrate

“…The misalignment of the two patterned SiO 2 trenches was designed to enhance the block of the defects. Regular semielliptical voids are formed at the top of the SiO 2 trenches as a result of the coalescence of the Ge overgrowth [ 30 ]. These voids indicate perfect coalesced Ge layer forms [ 46 , 47 ].…”

“…The dislocation defects generate at the interface and move into the Ge layer. These defects may cause a serious degradation in electronic and optical performance [ 29 , 30 ]. Intensive efforts have been engaged to reduce the defects density in the Ge epilayer.…”