A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells

Shimizu,; Naito,; Itoh,; Shibata,; Hashimoto, Y.; Nishio,; Asai, Hideki; Ohe,; Umimoto,; Hirofuji,

doi:10.1109/iedm.1992.307360

Cited by 11 publications

(4 citation statements)

References 5 publications

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“…Although initially there were doubts about the scalability of the technology beyond 1 mm, ingenious approaches such as polybuffered LOCOS [11] and polybuffered recessed LOCOS [12] extended it even to 0.25 mm [10]. Such a technology is shallow trench isolation, which relies on reactive ion etching (RIE) and chemical vapor deposition (CVD) oxide filled trenches as isolation rather than areas formed by oxidation.…”

Section: Locos To Stimentioning

confidence: 99%

Shallow Trench Isolation Chemical Mechanical Planarization

Stefanov

Schwalke

2007

Microelectronic Applications of Chemical Mechanical Planarization

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Section: Locos To Stimentioning

confidence: 99%

Shallow Trench Isolation Chemical Mechanical Planarization

Stefanov

Schwalke

2007

Microelectronic Applications of Chemical Mechanical Planarization

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“…1,2 Traditionally, local oxidation of silicon (LOCOS) 3,4 had been adopted as the standard technology for device geometry above 0.5 m. However, the lateral oxidation encroachment (bird's beak) into active area prevents LOCOS from scaling down to device dimensions of 0.25 m and below, even with its alternative techniques, such as self-aligned LOCOS/trench 5 and poly-buffer LOCOS. 6,7 As dimensions shrink, STI technology exhibits its superior advantages to meet the critical requirements for device scalability, which includes (i) abrupt transition from active MOSFET to isolation regions; (ii) independence of isolation width and depth; and (iii) concurrently achieving planarity. 8 Possible STI process integration schemes have been discussed in some of the early publications.…”

mentioning

confidence: 99%

High Temperature Subatmospheric Chemical Vapor Deposited Undoped Silicate Glass: A Solution for Next Generation Shallow Trench Isolation

Xia

Nemani

Galiano

et al. 1999

J. Electrochem. Soc.

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Undoped silicate glass deposited using the tetraethylorthosilicate (TEOS) and ozone thermal reaction has been selected as one of the candidates for shallow trench isolation applications. As a replacement for existing low pressure or atmospheric pressure chemical vapor deposition processes for device dimensions below 0.25 μm, TEOS/ozone films deposited at high temperature (>550°C) exhibit the superior qualities in terms of void‐free trench fill. In this paper, we present some characterization of the silicon oxide film deposited in the subatmospheric pressure regime using TEOS/ozone chemistry, aimed at developing a high‐quality dielectric film to meet shallow trench isolation gap‐fill requirements. It is also identified that low ozone/TEOS ratio reduces surface and pattern sensitivity. Therefore, no additional treatment or predeposition is necessary. Moreover, to enhance the etch resistance of the silicon oxide, the as‐deposited film is annealed at high temperature for densification and bond reconstruction. © 1999 The Electrochemical Society. All rights reserved.

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“…Besides the associated process complexity (and thus the higher manufacturing cost) and the successful scaling of LOCOStype isolation to 0.25pm technology node [7], trench isolation by oxide refill has long been noted to have trench edge enhanced electric field effects, resulting from the over-etch of trench lining oxide. Typical edge effects include subthreshold double hump phenomena [3,6] or inverse narrow width effects [Z].…”

Section: Introductionmentioning

confidence: 99%

A trench isolation study for deep submicron CMOS technology

Chen

Rödder

Chatterjee

et al.

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

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A b s t r a c tThe simple approach of thermal oxide capped poly refill trench isolation [l] is studied with regard to the impact of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation characteristics. It is shown that an increase of cap oxide thickness (to=) from 600 to 2OOOA eliminates subthreshold double-hump phenomena, improves isolation VT, improves inverse narrow-width effect, and still maintains reasonably low diode leakage current. An improvement of isolation VT is observed with thinner thermal oxide (-50A) on trench wall due to the less dopant segregation, while diode leakage is found to be insensitive to the trench wall thermal oxide thickness. The trade-off between latch-up holding and MOSFET snapback voltages leads to an optimal trench depth. I n t r o d u c t i o nTrench isolation has long been regarded as a successor to LOCOS (Local Oxidation of Silicon) type isolation due to its relatively smaller physical encroachment (or bird's beak), larger isolation distance (due to trench depth), and higher latch-up immunity compared to those of a LOCOS-type isolation [l-71. However, as yet, trench isolation has hardly been used in CMOS products despite these advantages. Besides the associated process complexity (and thus the higher manufacturing cost) and the successful scaling of LOCOStype isolation to 0.25pm technology node [7], trench isolation by oxide refill has long been noted to have trench edge enhanced electric field effects, resulting from the over-etch of trench lining oxide. Typical edge effects include subthreshold double hump phenomena [3,6] or inverse narrow width effects [Z]. Various approaches were proposed to reduce these undesirable edge effects, e.g. 1) additional trench sidewall doping by either trench sidewall implant [2] or diffusion [3], 2) a T-shaped refill-oxide trench isolation structure [4], 3) an oxide-poly-oxide field-shield on the trench sidewall together with chemical-mechanical polish (CMP) to avoid sidewall oxide loss [5], and 4) a trench-after-gate process to avoid sidewall oxide loss [6]. However, trench sidewall doping is undesiiable for scaled devices of which the device width is comparable to twice the diffusion depth of the sidewall doping. Both the T-shaped refill-oxide and the oxide-polyoxide field-shield plus CMP planarization process are quite complicated. The trench-after-gate process may damage the gate oxide quality. In this study, we revisit the simple thermal oxide capped poly refill trench isolation process [l] and investigate the impacts of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation Characteristics.S a m p l e P r e p a r a t i o n a n d Characterization A 0.4pm CMOS technology is used to study the oxidecapped poly-refilled trench isolation. The starting material waa p t y p e 2-5x 1015 cm-3 (100)-oriented non-epi Si wafer. After CM05 well formation, apodified scaled LOCOS with 5500A field oxide was formed for isolating active regions >.8pm apart. After a 15...

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A poly-buffer recessed LOCOS process for 256 Mbit DRAM cells

Cited by 11 publications

References 5 publications

Shallow Trench Isolation Chemical Mechanical Planarization

Shallow Trench Isolation Chemical Mechanical Planarization

High Temperature Subatmospheric Chemical Vapor Deposited Undoped Silicate Glass: A Solution for Next Generation Shallow Trench Isolation

A trench isolation study for deep submicron CMOS technology

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