A Platform-Based SoC Design of a 32-Bit Smart Card

Kim, Wonjong; Kim, Seungchul; Bae, Younghwan; Jun, Sungik; Park, Young-Soo; Cho, Hanjin

doi:10.4218/etrij.03.0103.0026

Cited by 18 publications

(8 citation statements)

References 8 publications

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“…Under these conditions, the more strongly adsorbed adsorbate displaces the weaker adsorbate, leading to a rise in the outlet concentration of the less strongly adsorbed adsorbate above the inlet concentration. For binary vapor system of benzene and toluene on activated carbon bed, toluene is more strongly adsorbed than benzene [30]. This result could be explained by the fact that the affinity difference between silica-alumina and adsorbates, acetone and toluene.…”

Section: Comparison Of Breakthrough Curves Of Binary Vapor System Commentioning

confidence: 61%

“…This result was similar to the breakthrough characteristics according to changes of inlet concentration. This result can be explained that the more linear velocity is increased, the more adsorbates per unit time are flowed into adsorption bed, and the vapor film on the surface of silica-alumina becomes thin, thus mass transfer coefficient of vapor film is increased and adsorption velocity is faster [29,30].…”

Section: Effect Of Linear Velocity Of Adsorbate On Breakthrough Curvementioning

confidence: 80%

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Comparison of adsorption characteristics according to polarity difference of acetone vapor and toluene vapor on silica–alumina fixed-bed reactor

Lee

Park

Lee

et al. 2008

Journal of Industrial and Engineering Chemistry

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Section: Comparison Of Breakthrough Curves Of Binary Vapor System Commentioning

confidence: 61%

Section: Effect Of Linear Velocity Of Adsorbate On Breakthrough Curvementioning

confidence: 80%

Comparison of adsorption characteristics according to polarity difference of acetone vapor and toluene vapor on silica–alumina fixed-bed reactor

Lee

Park

Lee

et al. 2008

Journal of Industrial and Engineering Chemistry

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“…The DRAM cell consists of an access transistor which is biased to 2.5 V during operation and an NMOS capacitor having a capacitance of 10 fF per unit cell. Its cell size is 3.63 µm 2 . The cell is optimized to minimize the leakage current.…”

Section: Discussionmentioning

confidence: 99%

“…An open bit line structure is used to reduce the block size. The areas of the unit cell and capacitor are 3.63 and 1.59 µm 2 , respectively. To obtain maximum cell capacitance, spacing in adjacent active regions of the memory cell has a shorter distance than in the normal logic rule.…”

Section: Introductionmentioning

confidence: 99%

“…The advantages of embedding DRAM to logic circuits are an increased bandwidth [2], [3], reduced power consumption, and small die size. However, there are critical problems such as a degraded refresh time in the DRAM cell and a low yield caused by the increase in processing steps when one embeds a conventional DRAM cell to the logic process [4].…”

Section: Introductionmentioning

confidence: 99%

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Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

Lee¹,

Jeon²,

Chang³

2004

ETRI J

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In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm 2 . We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when V cc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.Keywords: DRAM, noise margin, planar cell, refresh time, shielded metal line. Manuscript received Nov. 25, 2003; revised June 23, 2004. Junghwan Lee (phone: +82 43 270 3930, email: junghwan.lee@magnachip.com) and Seongdo Jeon (email: seongdo.jeon@magnachip.com) are with the SoC Device Team, MagnaChip Semiconductor Inc., Cheongju, Korea.Sung-Keun Chang (email: skchang@chungwoon.ac.kr) is with the Department of Electronics Engineering, Chungwoon University, Hongseong, Korea. I. IntroductionThere has been increasing interest in embedded DRAM for system-on-chip application [1]. The advantages of embedding DRAM to logic circuits are an increased bandwidth [2], [3], reduced power consumption, and small die size. However, there are critical problems such as a degraded refresh time in the DRAM cell and a low yield caused by the increase in processing steps when one embeds a conventional DRAM cell to the logic process [4]. This is caused by incompatibility between DRAM and the logic process. While the DRAM process focuses on the reduction of cell size with a sacrifice in device performance, the logic process mainly focuses on increasing device performance by using a dual gate transistor, salicide, and multi-level metals. Unfortunately, those steps in the logic process degrade the refresh time of the DRAM cell and also reduce the total yield due to the increase in process steps. Therefore, one should modify the conventional logic process when a conventional DRAM cell is embedded. This results in a modification of the logic library and intellectual properties (IPs) since they were proved using the conventional logic process.Recently, a planar DRAM cell has been investigated to solve these problems [5], [6]. A planar DRAM cell consists of one access transistor and MOS capacitor with a metal bit line. Although its cell size is normally four to seven times larger than a stack or trench type DRAM cell, it uses a conventional logic process and thus enables the use of the conventional logic library and IPs. When a new DRAM cell is developed, two major parameters should be optimized. The first is the refresh In this paper, we report on the influence of a shield bit line with a gro...

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Design and Implementation of Crypto Co-processor and Its Application to Security Systems

Kim

Lee

Kim

et al. 2005

Computational Intelligence and Security

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A Platform-Based SoC Design of a 32-Bit Smart Card

Cited by 18 publications

References 8 publications

Comparison of adsorption characteristics according to polarity difference of acetone vapor and toluene vapor on silica–alumina fixed-bed reactor

Comparison of adsorption characteristics according to polarity difference of acetone vapor and toluene vapor on silica–alumina fixed-bed reactor

Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application

Design and Implementation of Crypto Co-processor and Its Application to Security Systems

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