In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of 3.63 µm 2 . We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when V cc is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.Keywords: DRAM, noise margin, planar cell, refresh time, shielded metal line. Manuscript received Nov. 25, 2003; revised June 23, 2004. Junghwan Lee (phone: +82 43 270 3930, email: junghwan.lee@magnachip.com) and Seongdo Jeon (email: seongdo.jeon@magnachip.com) are with the SoC Device Team, MagnaChip Semiconductor Inc., Cheongju, Korea.Sung-Keun Chang (email: skchang@chungwoon.ac.kr) is with the Department of Electronics Engineering, Chungwoon University, Hongseong, Korea. I. IntroductionThere has been increasing interest in embedded DRAM for system-on-chip application [1]. The advantages of embedding DRAM to logic circuits are an increased bandwidth [2], [3], reduced power consumption, and small die size. However, there are critical problems such as a degraded refresh time in the DRAM cell and a low yield caused by the increase in processing steps when one embeds a conventional DRAM cell to the logic process [4]. This is caused by incompatibility between DRAM and the logic process. While the DRAM process focuses on the reduction of cell size with a sacrifice in device performance, the logic process mainly focuses on increasing device performance by using a dual gate transistor, salicide, and multi-level metals. Unfortunately, those steps in the logic process degrade the refresh time of the DRAM cell and also reduce the total yield due to the increase in process steps. Therefore, one should modify the conventional logic process when a conventional DRAM cell is embedded. This results in a modification of the logic library and intellectual properties (IPs) since they were proved using the conventional logic process.Recently, a planar DRAM cell has been investigated to solve these problems [5], [6]. A planar DRAM cell consists of one access transistor and MOS capacitor with a metal bit line. Although its cell size is normally four to seven times larger than a stack or trench type DRAM cell, it uses a conventional logic process and thus enables the use of the conventional logic library and IPs. When a new DRAM cell is developed, two major parameters should be optimized. The first is the refresh In this paper, we report on the influence of a shield bit line with a gro...
High-performance 0.1-µm-gate InP-based enhancement-mode high electron mobility transistors (E-HEMTs) were fabricated using two-step-recessed-gate technology, where the gate recess etching is first carried out by wet-chemical etching to removed n + -cap layers and then by Ar plasma etching to remove the InP etch stopper layer. Etching selectivies for both steps are sufficient not to degrade the uniformity of the device characteristics. The main advantage over the conventional approach for E-HEMTs, Pt-based-gate technology, is the fact that the stability of the threshold voltage is improved by means of a refractory gate metal, WSiN. The change in the threshold voltage is only 50 mV after 160-h bias and thermal stress at 195 • C.
This paper describes a novel bipolar technology, the Schottky-Base I L, which offers significant advantages in terms of packing density, device performance, and reduced LS circuit complexity as compared to conventional I L designs. A pnp transistor fabricated in an n-epitaxial layer on a ptsubstrate forms the active switch for this design. Current source to the pnp is provided by an npn transistor. Schottky diodes are formed on the pnp base which is merged with the npn(injector) collector. Hence, the basic logic gate in this des i g n i s a multi-input, multi-output NAND gate. B e c a u s e a n n -o n -p t y p e s t r u c t u r e i s u s e d , T T L , STTL, or ECL circuits can be made readily available on chip. Design trade-offs for optimizing the speed-power performance are described. Experimental data on a test chip indicate pnp c u rrent gain of -80 and a minimum delay of 10 n s of the SB12L gate using 7.5 pm minimum linewidths. 2 z
We propose the equivalent circuit model including all parasitic components in input gate of sense amplifier of DDI DRAM with butting contact structure. We analysed the effect of parasitic schottky diode by using the proposed model in the operation of sense amplifier. The cause of single side fail and the temperature dependence of fail rate in DDI DRAM are due to creation of the parasitic schottky diode in input gate of sense amplifier. The parasitic schottky diode cause the voltage drop in input gate, and result in decreasing noise margin of sense amplifier. therefore single side fail rate increase.
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