Characteristics of Dual Polymetal (W/WNx/Poly-Si) Gate Complementary Metal Oxide Semiconductor for 0.1 µm Dynamic Random Access Memory Technology

Abstract

High-performance 0.1-µm-gate InP-based enhancement-mode high electron mobility transistors (E-HEMTs) were fabricated using two-step-recessed-gate technology, where the gate recess etching is first carried out by wet-chemical etching to removed n + -cap layers and then by Ar plasma etching to remove the InP etch stopper layer. Etching selectivies for both steps are sufficient not to degrade the uniformity of the device characteristics. The main advantage over the conventional approach for E-HEMTs, Pt-based-gate technology, is the fact that the stability of the threshold voltage is improved by means of a refractory gate metal, WSiN. The change in the threshold voltage is only 50 mV after 160-h bias and thermal stress at 195 • C.