A planar gate double beryllium implanted GaAs power MESFET for low voltage digital wireless communication application

Abstract

An ion-implanted planar gate power MESFET for low voltage digital wireless communication system including DCS1800 (digital cellular system at 1800 MHz) and CDMA (code division multiple access) handset applications has been developed. The process for the device developed contains double Be implantation to reduce the surface and substrate defect trapping effects. The MESFET process developed has very little gate recess (less than 200 Angstrom), which greatly improves the uniformity and the yield of the wafer, The 1 mu m x 20 mm MESFET manufactured using this planar gate technology exhibits an output power of 32.98 dBm and power added efficiency over 53% with gain of 11.2 dB when tested at 1.9 GHz under 3.6 V drain bias voltage and 80 mA quiescent drain current. The pinch off voltage of the 20 mm devices within a wafer is -2.81 V with a standard deviation of 120 mV, The device was also tested at 3.6 V and 1.9 GHz for CDMA application. Under the IS-95 CDMA modulation at 28 dBm output power, the device gain is 10.7 dB and the device has an adjacent channel power rejection (ACPR) of -29.5 dBc at 1.25 MHZ offset frequency and -44.9 dBc at 2.25 MHz offset. The test data shows that the double Be implanted devices developed using the planar gate technology have very good linearity and efficiency and can be used for the low voltage DCS1800 and CDMA handset applications

Characteristics of GaAs Power MESFETs with Double Silicon Ion Implantations for Wireless Communication Applications

“…The GaAs power MESFETs were fabricated with double 29 Si + -ion implantations into a semi-insulating GaAs wafer.…”

“…Channel implantation was conducted by 29 Si + ion implantation with an energy of 200 keV and a dosage of 3.0 × 10 12 cm -2 to form a channel layer with high current capability. Surface implantation was implemented by 29 Si + ion implantation with an energy of 50 keV and a dosage of 1.0 × 10 12 cm -2 to form a low-resistivity ohmic layer.…”

“…Surface implantation was implemented by 29 Si + ion implantation with an energy of 50 keV and a dosage of 1.0 × 10 12 cm -2 to form a low-resistivity ohmic layer.…”

“…The GaAs wafer was sputtered with silicon nitride film for the passivation process after double 29 Si + -ion implantations. The passivation process was used to prevent the decomposition of the GaAs material and the loss of arsenic atoms during the subsequent activation process with high-temperature annealing.…”

“…A 2.2-V-operation GaAs power MESFET with a gate width of 2 mm demonstrated an adjacent channel power rejection (ACPR) of -58 dBc and a PAE of 57.2% at a P out of 21.3 dBm. A planar-gate GaAs power MESFET with direct Si and Be ion implantations also showed good characteristics at 3.6 V [29]. GaAs power MESFETs with direct ion implantations provide a cost-effective solution for digital wireless communications [30].…”