A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

Benschneider, B.J.; Bowhill, William J.; Copper, E.M.; Gavrielov, Moshe; Gronowski, P.E.; Maheshwari, Vikas; Peng, V.; Pickholtz, J.D.; Samudrala, S.

doi:10.1109/jssc.1989.572606

Cited by 19 publications

(5 citation statements)

References 6 publications

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“…A hybrid radix-4/-8 is proposed in [3] for low-power multimedia applications. To increase the speed of the multiplier, most ancient processors employed radix-8, such as: Fchip [4], IBM S/390 [5], Alpha RISC [6], IA-32 [7] and AMDK7 [8]. While radix-16 is used only in the most recent Intel processors: 64 and IA-32 [9], and Itanium-Poulson [10].…”

Section: Background and Motivationmentioning

confidence: 99%

“…In case r is not a multiple of 8, optimal solutions are also obtained, composed mainly of radix-2 8 algorithm with at most one instance of radix-2 1 , 2 2 or 2 5 algorithms, depending on the remainder of r by 8 division. 8 A -T 0 0 4 0 3 40 3 40 A -AT 5 0 0 8 0 7 80 16 T 0 3 0 1 5 404 5 80 A -AT 3 0 0 16 0 15 160 32 AT 4 A -T: all the metric span A, A 5 T, A 4 T, A 3 T, A 2 T, AT, AT 2 , AT 3 , AT 4 , AT 5 , T. To A and T metrics correspond respectively the minimal values Mux min and Del min that serve as reference for the optimization process. 5 2 25 2 8 3 40 The new results are so interesting that we are encouraged to pursue further the optimization process using higher basic sub-radices (s>8) to reduce the total delay (Del T ) of the multiplier.…”

Section: Preliminary Study To An Optimal Partitionningmentioning

confidence: 99%

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A new high radix-2 ^r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers

Oudjida¹,

Chaillet²,

Berrandjia³

et al. 2012

SIGARCH Comput. Archit. News

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This paper addresses the problem of multiplication with large operand sizes (N≥32). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture for any size N of the operands. As a result, the critical path is drastically reduced to 3 2 3 3 − / N with no area overhead in comparison to modified Booth algorithm that shows a critical path of N/2 in adder stages. For instance, only 7 adder stages are needed for a 64-bit two's complement multiplier. Confronted to reference algorithms for N=64, important gain ratios of 1.62, 1.71, 2.64 are obtained in terms of multiply-time, energy consumption per multiplyoperation, and total gate count, respectively.

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Section: Background and Motivationmentioning

confidence: 99%

Section: Preliminary Study To An Optimal Partitionningmentioning

confidence: 99%

A new high radix-2 ^r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers

Oudjida¹,

Chaillet²,

Berrandjia³

et al. 2012

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

show abstract

“…when CPU clock frequencies rose swiftly: from 50 MHz in 1989 [2], clocks reached 200 MHz in 1992 [3] and 1 GHz in 2000 [4], before eventually saturating between 3 and 5 GHz since 2001 [5]- [7]. The concomitant near exponential rise in power density (dissipated power per unit chip area, in W/cm 2 ) reached ∼100 W/cm 2 in 2004 [8], where it also saturated with the introduction of multicore CPU architectures.…”

mentioning

confidence: 99%

High-Speed Steep-Slope GaInAs Impact Ionization MOSFETs (I-MOS) With SS = 1.25 mV/dec—Part I: Material and Device Characterization, DC Performance, and Simulation

Han¹,

Bonomo²,

Ruiz³

et al. 2022

IEEE Trans. Electron Devices

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Digital electronics power consumption evolved into a major concern: at the current pace, generalpurpose computing energy consumption will exceed global energy production before 2045. The principal approach to curbing energy consumption in digital applications calls for "steep-slope" devices with an inverse subthreshold slope (SS) parameter well below the "ln(10)•kT /q" limit of conventional electronics ( 60mV/dec at 300 K). Impact ionization MOSFETs (I-MOS) provide an avenue for steepslope device realization. High-mobility narrow gap III-V semiconductor channel materials have not yet been investigated for I-MOS applications. We hereby report E-mode narrow bandgap GaInAs-based I-MOS devices with an SS of 1.25 mV/dec maintained over five orders of magnitude in drain current and I ON /I OFF ratios >10 6 at 300 K (>10 9 at 15 K) for a gate length of L G = 100 nm. Part I of this work focuses on the materials and device fabrication and analysis, device dc characterization, and modeling. The present GaInAs devices are the first I-MOS transistors to display a robust steep-slope effect at low voltages V DS < 1.9 V at 300 K and <1 V at 15 K. Part II describes the dynamic switching (including clarifications on the role of hysteresis) and RF characteristics of GaInAs I-MOS devices and benchmarks them with respect to other steep-slope technologies.

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mentioning

confidence: 99%

A New High Radix-2r (r ≥ 8) Multibit Recoding Algorithm for Large Operand Size (N ≥ 32) Multipliers

Oudjida¹,

Chaillet²,

Berrandjia³

et al. 2013

Journal of Low Power Electronics

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A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

Cited by 19 publications

References 6 publications

A new high radix-2 ^r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers

A new high radix-2 ^r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers

High-Speed Steep-Slope GaInAs Impact Ionization MOSFETs (I-MOS) With SS = 1.25 mV/dec—Part I: Material and Device Characterization, DC Performance, and Simulation

A New High Radix-2<SUP>r</SUP> (<I>r</I> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<I>N</I> ≥ 32) Multipliers

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A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

Cited by 19 publications

References 6 publications

A new high radix-2 r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers

A new high radix-2 r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers

High-Speed Steep-Slope GaInAs Impact Ionization MOSFETs (I-MOS) With SS = 1.25 mV/dec—Part I: Material and Device Characterization, DC Performance, and Simulation

A New High Radix-2<SUP>r</SUP> (<I>r</I> ≥ 8) Multibit Recoding Algorithm for Large Operand Size (<I>N</I> ≥ 32) Multipliers

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A new high radix-2 ^r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers

A new high radix-2 ^r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers