A performance and energy comparison of convolution on GPUs, FPGAs, and multicore processors

Fowers, Jeremy; Brown, G.R.; Wernsing, John; Stitt, Greg

doi:10.1145/2400682.2400684

Cited by 30 publications

(26 citation statements)

References 24 publications

(28 reference statements)

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“…Numerous earlier studies have evaluated FPGA performance for sliding-window applications, showing a variety of performance and energy advantages and trade-offs compared to microprocessors [Guo et al 2004] and GPUs [Fowers et al 2013;Baker et al 2007;Cope et al 2005;Asano et al 2009Pauwels et al 2012. The presented approach is complementary to these previous studies, potentially enabling significantly better FPGA performance via parallel windows.…”

Section: Previous Workmentioning

confidence: 95%

“…For 2D convolution, these values will commonly be small (e.g., 3×3 and 5×5). A 1D convolution uses a single row, but the maximum window columns would be as large as the kernel, which commonly requires thousands of elements [Fowers et al 2013]. For image-comparison applications (e.g., template matching), the maximum window dimensions would be as large as the maximum dimensions of all tested images.…”

Section: Configuration Optionsmentioning

confidence: 99%

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A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

Stitt

Schwartz

Cooke

2016

ACM Trans. Reconfigurable Technol. Syst.

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Sliding-window applications, an important class of the digital-signal processing domain, are highly amenable to pipeline parallelism on field-programmable gate arrays (FPGAs). Although memory bandwidth often restricts parallelism for many applications, sliding-window applications can leverage custom buffers, referred to as sliding-window generators, that provide massive input bandwidth that far exceeds the capabilities of external memory. Previous work has introduced a variety of sliding-window generators, but those approaches typically generate at most one window per cycle, which significantly restricts parallelism. In this article, we address this limitation with a parallel sliding-window generator that can generate a configurable number of windows every cycle. Although in practice the number of parallel windows is limited by memory bandwidth, we show that even with common bandwidth limitations, the presented generator enables near-linear speedups up to 16x faster than previous FPGA studies that generate a single window per cycle, which were already in some cases faster than graphics-processing units and microprocessors. . 2016. A parallel sliding-window generator for high-performance digital-signal processing on FPGAs. ACM Trans.

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Section: Previous Workmentioning

confidence: 95%

Section: Configuration Optionsmentioning

confidence: 99%

A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

Stitt

Schwartz

Cooke

2016

ACM Trans. Reconfigurable Technol. Syst.

Self Cite

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“…A thorough investigation of 1D convolution across different platforms is done in [Fowers et al 2013]. The 1D convolution is implemented in both time-domain using the overlap-save algorithm and frequency-domain using the overlap-save algorithm.…”

Section: One-dimensional Convolutionmentioning

confidence: 99%

FPGA-based Acceleration of FT Convolution for Pulsar Search Using OpenCL

Wang

Prabu

Sinnen

2018

ACM Trans. Reconfigurable Technol. Syst.

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The Square Kilometre Array (SKA) project will be the world largest radio telescope array. With its large number of antennas, the number of signals that need to be processed is dramatic. One important element of the SKA's Central Signal Processor package is pulsar search. This paper focuses on the FPGA-based acceleration of the Frequency-Domain Acceleration Search module, which is a part of SKA pulsar search engine. In this module, the frequency-domain input signals have to be processed by 85 Finite Impulse response (FIR) filters within a short period of limitation and for thousands of input arrays. Because of the large scale of the input length and FIR filter size, even high-end FPGA devices cannot parallelise the task completely. We start by investigating both time-domain FIR filter (TDFIR) and frequency-domain FIR filter (FDFIR) to tackle this task. We applied the overlap-add algorithm to split the coefficient array of TDFIR and the overlap-save algorithm to split the input signals of FDFIR. To achieve fast prototyping design, we employed OpenCL, which is a high-level FPGA development technique. The performance and power consumption are evaluated using multiple FPGA devices simultaneously and compared with GPU results, which is achieved by porting FPGA-based OpenCL kernels. The experimental evaluation shows that the FDFIR solution is very competitive in terms of performance, with a clear energy consumption advantage over the GPU solution.

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“…Jeremy Fowers et al studied the 1D convolution for image processing on the CPU, GPU and FPGA platforms [9] .…”

Section: Related Workmentioning

confidence: 99%

A heterogeneous platform with GPU and FPGA for power efficient high performance computing

Kumar

et al. 2014

2014 International Symposium on Integrated Circuits (ISIC)

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Heterogeneous computing is gaining attention from both industry and academia nowadays. One driving factor for heterogeneous computing is the power efficiency. GPU and FPGA have been reported to achieve much higher power efficiency over CPU on many applications. Comparisons between GPU and FPGA show different characteristics of GPU and FPGA in accelerated computing. Some tasks run better on GPU, some run better on FPGA. Combining GPU and FPGA in one heterogeneous computing platform may provide us the advantages from both sides. This paper presents a heterogeneous computing platform with GPU and FPGA that we have built for power efficient high performance computing. The experimental results of 4 application examples show that different applications have different favorite computing architectures, which suggests a matching of the characteristics between the computation task and the computing architecture is the key to the power efficient high performance computing on heterogeneous computing platforms.

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A performance and energy comparison of convolution on GPUs, FPGAs, and multicore processors

Cited by 30 publications

References 24 publications

A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs

FPGA-based Acceleration of FT Convolution for Pulsar Search Using OpenCL

A heterogeneous platform with GPU and FPGA for power efficient high performance computing

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