A heterogeneous platform with GPU and FPGA for power efficient high performance computing

Wu, Qiang; Ha, Yajun; Kumar, Akash; Luo, Shaobo; Li, Ang; Mohamed, Shihab

doi:10.1109/isicir.2014.7029447

Cited by 16 publications

(3 citation statements)

References 11 publications

(8 reference statements)

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“…GPU performance decreases with increasing kernel size, but there is no single platform that is always most suitable and the data flow of the desired algorithm must always be considered. Wu et al [20] reinforce these conclusions while taking power into account.…”

Section: Platform Selection and Power-aware Computingmentioning

confidence: 80%

Video Anomaly Detection in Real Time on a Power-Aware Heterogeneous Platform

Blair

Robertson

2016

IEEE Trans. Circuits Syst. Video Technol.

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Field-programmable gate arrays (FPGAs) and graphics processing units (GPUs) are often used when real-time performance in video processing is required. An accelerated processor is chosen based on task-specific priorities (power consumption, processing time, and detection accuracy), and this decision is normally made once at design time. All three of the characteristics are important, particularly in battery-powered systems. Here, we propose a method for moving selection of processing platform from a single design-time choice to a continuous run-time one. We implement Histogram of Oriented Gradients (HOG) for cars and people and Mixture-of-Gaussians motion detectors running across FPGA, GPU, and central processing unit in a heterogeneous system. We use this to detect illegally parked vehicles in urban scenes. Power, time, and accuracy information for each detector is characterized. An anomaly measure is assigned to each detected object based on its trajectory and location compared with learned contextual movement patterns. This drives processor and implementation selection so that scenes with high behavioral anomalies are processed with faster but more power-hungry implementations, but routine or static time periods are processed with power-optimized and less accurate slower versions. Real-time performance is evaluated on video data sets including i-LIDS. Compared with power-optimized static selection, automatic dynamic implementation mapping is 10% more accurate, but draws 12-W of extra power in our testbed desktop system.

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Section: Platform Selection and Power-aware Computingmentioning

confidence: 80%

Video Anomaly Detection in Real Time on a Power-Aware Heterogeneous Platform

Blair

Robertson

2016

IEEE Trans. Circuits Syst. Video Technol.

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“…SnuCL also proposes [12] an OpenCL framework for heterogeneous CPU/GPU clusters, considering how to combine clusters with different GPU and CPU hardware under a single OS image. Clusters of independent devices have also been studied in papers such as [13]. Their experimental results based on four application examples confirm that different applications have different favorite computing architectures.…”

Section: Background and Related Workmentioning

confidence: 99%

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs

Rodríguez

Navarro

Asenjo

et al. 2019

Journal of Systems Architecture

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This paper presents a framework targeted to low-cost and low-power heterogeneous MultiProcessors that exploits FPGAs and multicore CPUs, with the overarching goal of providing developers with a productive programming model and runtime support to fully use all the processing resources available. FPGA productivity is achieved using a high-level programming model based on OpenCL, the standard for cross-platform parallel heterogeneous programming. In this work, we focus on the parallel for pattern, and as part of the runtime support for this pattern, we leverage a new scheduler that strives to maximize the number of iterations per joule by dynamically and adaptively partitioning the iteration space between the multicore and the accelerator when working simultaneously. A total of 7 benchmarks are ported and optimized for a low-cost DE1 board. The results show that the heterogeneous solution can improve performance up to 2.9x and increases energy efficiency up to 2.7x compared to the traditional approach of keeping all the CPU cores idle while the accelerator computes the workload. Our results also demonstrate two interesting insights: first, an adaptive scheduler able to find at runtime the right chunk size for each type of application and device configuration is an essential component for these kinds of heterogeneous platforms, and second, device configurations that provide higher throughput do not always achieve better energy efficiency when only the running power (excluding the idle power component) is considered.

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“…That is the core computations are divided into distinct algorithms and mapped to the accelerators, which are best suited for executing these algorithms. Wu et al [28] build a heterogeneous computing platform composed from multicore CPUs, GPUs, and FPGAs to understand how to map an application to the various architectures with an objective of maximizing energy efficiency.…”

Section: A Hpc 2 Platformsmentioning

confidence: 99%

A Hierarchical Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous Multi-Accelerator NUMA Nodes

2020

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Modern HPC platforms are highly heterogeneous with tight integration of multicore CPUs and accelerators (such as Graphics Processing Units, Intel Xeon Phis, or Field-Programmable Gate Arrays) empowering them to address the twin critical concerns of performance and energy efficiency. Due to this inherent characteristic, processing elements contend for shared on-chip resources such as Last Level Cache (LLC), interconnect, etc. and shared nodal resources such as DRAM, PCI-E links, etc., resulting in complexities such as resource contention, non-uniform memory access (NUMA), and accelerator-specific limitations such as limited main memory thereby necessitating support for efficient out-of-card execution. Due to these complexities, the performance profiles of data-parallel applications executing on these platforms are not smooth and deviate significantly from the shapes that allowed state-of-the-art load-balancing algorithms to find optimal solutions. In this paper, we propose a hierarchical two-level data partitioning algorithm minimizing the parallel execution time of data-parallel applications on clusters of h identical nodes where each node has c heterogeneous processors. This algorithm takes as input c discrete speed functions of cardinality m corresponding to the c heterogeneous processors. It does not make any assumptions about the shapes of these functions. Unlike load balancing algorithms, optimal solutions found by the algorithm may not load-balance an application in terms of execution time. The proposed algorithm has low time complexity of O(m 2 × h + m 3 × c 3 ) unlike the state-of-the-art algorithm solving the same problem with the complexity of O(m 3 × c 3 × h 3 ). We also propose an extension of the algorithm for clusters of h non-identical nodes where each node has c heterogeneous processors. We experimentally demonstrate the optimality of our algorithm using two well-known and highly optimized multi-threaded data-parallel applications, matrix-matrix multiplication and 2D fast Fourier transform, on a heterogeneous multi-accelerator NUMA node containing an Intel multicore Haswell CPU, an Nvidia K40c GPU, and an Intel Xeon Phi co-processor and a simulated homogeneous cluster of such nodes.

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A heterogeneous platform with GPU and FPGA for power efficient high performance computing

Cited by 16 publications

References 11 publications

Video Anomaly Detection in Real Time on a Power-Aware Heterogeneous Platform

Video Anomaly Detection in Real Time on a Power-Aware Heterogeneous Platform

Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs

A Hierarchical Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous Multi-Accelerator NUMA Nodes

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