Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs

Abstract

This paper presents a framework targeted to low-cost and low-power heterogeneous MultiProcessors that exploits FPGAs and multicore CPUs, with the overarching goal of providing developers with a productive programming model and runtime support to fully use all the processing resources available. FPGA productivity is achieved using a high-level programming model based on OpenCL, the standard for cross-platform parallel heterogeneous programming. In this work, we focus on the parallel for pattern, and as part of the runtime support for this pattern, we leverage a new scheduler that strives to maximize the number of iterations per joule by dynamically and adaptively partitioning the iteration space between the multicore and the accelerator when working simultaneously. A total of 7 benchmarks are ported and optimized for a low-cost DE1 board. The results show that the heterogeneous solution can improve performance up to 2.9x and increases energy efficiency up to 2.7x compared to the traditional approach of keeping all the CPU cores idle while the accelerator computes the workload. Our results also demonstrate two interesting insights: first, an adaptive scheduler able to find at runtime the right chunk size for each type of application and device configuration is an essential component for these kinds of heterogeneous platforms, and second, device configurations that provide higher throughput do not always achieve better energy efficiency when only the running power (excluding the idle power component) is considered.

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study

“…In recent years, the problem of real-time task execution on FPGAbased heterogeneous systems has gathered considerable attention from the research community. The generic problem of real-time scheduling tasks has branched out in different directions primarily based on: i) using optimizing frameworks [9], ii) using heuristic algorithms [10], and iii) using priority-driven algorithms [11]. In [9], the authors proposed a static partitioning-based scheduling strategy for CPU+FPGA systems to minimize energy consumption.…”

“…The generic problem of real-time scheduling tasks has branched out in different directions primarily based on: i) using optimizing frameworks [9], ii) using heuristic algorithms [10], and iii) using priority-driven algorithms [11]. In [9], the authors proposed a static partitioning-based scheduling strategy for CPU+FPGA systems to minimize energy consumption. In [12], the authors measured the speed-up in task execution on an FPGA and by utilizing their speed-up utilization model they determine the appropriate PE (i.e.…”