A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application

Mishra, Alok Kumar; Chopra, Urvashi; Vaithiyanathan, D.

doi:10.1109/tcsii.2021.3107684

Cited by 19 publications

(4 citation statements)

References 13 publications

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“…It is important to note that in the ACFF design, the width of the p-type pass transistor must be enlarged to provide better setup time to ensure its current operation. However, the ACFF design still cannot operate in the SF corner [ 24 , 25 ]. All input signals (clock and data) are generated after passing through the buffer circuit to account for the effects of rise time and fall time delays.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…With the development of new process technology, the design method of FF continues to develop. Specific application requirements such as low voltage, low power, low cost or high performance also require new designs [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 ]. In this work, the FF design goal is a low voltage and low power consumption with a compact layout area design solution.…”

Section: Introductionmentioning

confidence: 99%

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Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

Lin

Hong

et al. 2022

Sensors

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A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

Lin

Hong

et al. 2022

Sensors

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“…Several improved SAFF designs have been proposed, such as Jeong's SAFF [16], Strollo's SAFF [17], Zhang's SAFF [18], Nikolic's SAFF [14], Kim's SAFF [15], and Anoop's SAFF [25]. This paper proposes a new SAFF design based on the analysis of the above structure of SAFF and other previous SAFF [26]- [31]. The proposed SAFF uses a novel sense amplifier in the master stage, which avoids the redundant charge and discharge in node SN and RN with the CLK transition.…”

Section: Introductionmentioning

confidence: 99%

A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application

Yuan,

Zhao,

et al. 2023

IEICE Electron. Express

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This paper proposes a novel sense-amplifier-based flip-flop (SAFF) applied in low-power, high-speed operation. With the employment of the pre-charge control technique and shut-off transistor, the power and delay of the proposed SAFF are significantly reduced. Furthermore, the proposed SAFF can provide low-voltage operation. Post-layout simulation results based on the SMIC 55 nm CMOS process show that the proposed SAFF achieves a 28.9% reduction in the CLK-to-Q delay and a 53.2% decrease in power (25% input data switching activity) and the power-delayproduct of the proposed SAFF shows 3.0× improvement compared with the conventional SAFF.

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“…In fact, the possibilities of increasing speed by combining different circuit techniques in an available and relatively low-cost process have been investigated (Kawai et al , 2014; Varma et al , 2002). Figure 1 shows the block diagram of 18 T true single phase clocking (TSPC) which takes 18 transistors and a single clock (Cai et al , 2018; Mishra et al , 2021; Kumar Mishra et al , 2021). The main problem of this circuit is the higher clock to output delay.…”

Section: Introductionmentioning

confidence: 99%

A low power high speed single phase clock level restoring 16T master-slave flip-flop

Mishra

Chopra

Vaithiyanathan

et al. 2022

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Purpose A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops. Design/methodology/approach This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops. Findings The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop. Originality/value This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

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A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application

Cited by 19 publications

References 13 publications

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application

A low power high speed single phase clock level restoring 16T master-slave flip-flop

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