A parameterized VHDL library for on-line testing

Stroud, Charles E.; Ding, Mingyue; Seshadri, S.; Kim, I.; Roy, Suman; Wu, Shianling; Karri, Ramesh

doi:10.1109/test.1997.639654

Cited by 7 publications

(4 citation statements)

References 14 publications

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“…Another online testing method deals with utilizing coarse behavioral invariance either inherent in the design [7][8] or imposed through error detection codes [9][10], in order to check the correctness of the design functionality. In this case, while the circuit computes f(x) for input x, an additional function, g(x), with a well-defined, simple-to-check relation to f(x) is also computed.…”

Section: Introductionmentioning

confidence: 99%

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs

Karimi

Mirkhani

Navabi

2006

2006 15th Asian Test Symposium

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This paper proposes a novel and efficient method for RT Level online testing. Our method makes every RTLevel resource online-testable, and guarantees high single stuck-at fault detection (i.e., high reliability) with low area/latency overhead. This method uses available resources in their dead intervals (the intervals during which a resource is not being used) to test active resources. The area and/or latency overhead are due to concurrent operation of active and inactive resources. This method is evaluated by fault simulating several benchmark designs before and after applying the proposed algorithm. Experimental results show that after applying our method, online fault coverage is significantly improved.

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Section: Introductionmentioning

confidence: 99%

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs

Karimi

Mirkhani

Navabi

2006

2006 15th Asian Test Symposium

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“…Latency has not only been a difficult problem for on-line test methodologies to solve, but also hard to estimate. While some on-line test methods [2,11,14] guarantee zero-latency, they incur excessive area overhead, thus limiting their applicability. The invariance-based on-line test methodology proposed in [1] reduces the area overhead yet at the cost of introducing latency.…”

Section: Invariance Activation Frequencymentioning

confidence: 99%

“…Their applicability is consequently limited largely to combinational circuits. Approaches along the second direction utilize coarse behavioral invariance either inherent in the design [1,2] or imposed through error detection codes [11,14], in order to check the correctness of the functionality. In this case, while the circuit computes function f(x), an additional function, g(x), with a welldefined, simple-to-check relation to f(x), is also computed.…”

Section: Introductionmentioning

confidence: 99%

Invariance-based on-line test for RTL controller-datapath circuits

Makris

Bayraktaroglu

Orailoğlu

Proceedings 18th IEEE VLSI Test Symposium

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We present a low-cost on-line test methodology for RTL controller-datapath pairs, based on the notion of path invariance. The fundamental observation supporting the proposed methodology is that the transparency behavior inherent in RTL components renders rich sources of invariance in a design. Furthermore, the algorithmic controller-datapath interaction provides additional sources of invariance.judicious selection and combination of modular transparency, based on the algorithm implemented by the controller-datapath pair, yields a powerful set of invariant paths. Such paths enable a simple, yet very efficient on-line test capability, achieving fault security in excess of 90% while keeping the hardware overhead below 40% on complicated, difficult to test, benchmarks.

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“…Acting in the earlier steps of the design flow the designer can trade-off costs and dependability improvements, globally reducing the developing time. Possible approaches include synthesis techniques for self-checking combinational circuits [4] [5] [6], automatic generation of self-checking data paths using CAD tools [7]; libraries of VHDL components designed for high circuit reliability and availability [8] [9].…”

Section: Introductionmentioning

confidence: 99%

Automated synthesis of SEU tolerant architectures from OO descriptions

Chiusano

Carlo

Prinetto

Proceedings of the Eighth IEEE International on-Line Testing Workshop (IOLTW 2002)

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SEU faults are a well-known problem in aerospace environment but recently their relevance grew up also at ground level in commodity applications coupled, in this frame, with strong economic constraints in terms of costs reduction. On the other hand, latest hardware description languages and synthesis tools allow reducing the boundary between software and hardware domains making the high-level descriptions of hardware components very similar to software programs. Moving from these considerations, the present paper analyses the possibility of reusing Software Implemented Hardware Fault Tolerance (SIHFT) techniques, typically exploited in microprocessor based systems, to design SEU tolerant architectures. The main characteristics of SIHFT techniques have been examined as well as how they have to be modified to be compatible with the synthesis flow. A complete environment is provided to automate the design instrumentation using the proposed techniques, and to perform fault injection experiments both at behavioural and gate level. Preliminary results presented in this paper show the effectiveness of the approach in terms of reliability improvement and reduced design effort.

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A parameterized VHDL library for on-line testing

Cited by 7 publications

References 14 publications

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs

Invariance-based on-line test for RTL controller-datapath circuits

Automated synthesis of SEU tolerant architectures from OO descriptions

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