Invariance-based on-line test for RTL controller-datapath circuits

Makris, Yiorgos; Bayraktaroglu, I.; Orailoğlu, Alex

doi:10.1109/vtest.2000.843879

Cited by 9 publications

(6 citation statements)

References 17 publications

(21 reference statements)

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“…The proposed test generation methodology has been applied to the datapath portions of the GCD [23] and MAC [1] circuits, which consist of 9 and 20 high level modules, respectively. Table 3 provides the characteristics of the benchmark circuits.…”

Section: Resultsmentioning

confidence: 99%

Hierarchical constraint conscious RT-level test generation

Sinanoglu

Orailoğlu

2003

Euromicro Symposium on Digital System Design, 2003. Proceedings.

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The increasing complexity of ICs necessitates the use of test generation methodologies at higher levels of abstraction. We propose a computationally efficient RT-level test generation methodology that utilizes a divide and conquer approach. The hierarchical constraints for the module under test are identified through the proposed justification and propagation analysis. These constraints are then taken into account during the local test vector generation for the module under test, enabling the identification of the local test vectors that are guaranteed to be effective not only at the module-level but also at the system-level as well. High quality test sets are thus generated by the proposed methodology in a computationally efficient manner. Experimental results verify the performance boosts attained by the proposed methodology as well.

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Section: Resultsmentioning

confidence: 99%

Hierarchical constraint conscious RT-level test generation

Sinanoglu

Orailoğlu

2003

Euromicro Symposium on Digital System Design, 2003. Proceedings.

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“…A similar technique is proposed in [10], where the frequency response of linear filters is used as an invariance property, achieving a 50% cost reduction but introducing latency. Finally, a CFD approach exploiting transparency of RT-Level components is described in [11], achieving over 90% fault security with 40% hardware overhead.…”

Section: Related Workmentioning

confidence: 99%

Non-intrusive design of concurrently self-testable FSMs

Drineas

Makris

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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We propose a methodology for non-intrusive design of concurrently self-testable FSMs. The proposed method is similar to duplication, wherein a replica of the original FSM acts as a predictor that immediately detects potential faults by comparison to the original FSM. However, instead of duplicating the complete FSM, the proposed method replicates only a minimal portion adequate to detect all possible faults, yet at the cost of introducing potential fault detection latency. Furthermore, in contrast to concurrent error detection approaches, which presume the ability to resynthesize the FSM and exploit parity-based state encoding, the proposed method is non-intrusive and does not interfere with the encoding and implementation of the original FSM. Experimental results on FSMs of various sizes and densities indicate that the proposed method detects 100% of the faults with very low average fault detection latency. Furthermore, a hardware overhead reduction of up to 33% is achieved, as compared to duplication-based concurrent error detection.

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“…The proposed fault diagnosis methodology has been applied to the datapath portions of the MAC [11] and GCD [12] circuits, and the diagnostic resolution, storage size and run-time results have been compared to those of a pass-fail dictionary. Although the proposed methodology is independent of any specific fault model, for experimental purposes, diagnostic resolution levels are reported based on the stuck-at fault model.…”

Section: Resultsmentioning

confidence: 99%

Efficient RT-level fault diagnosis methodology

Sinanoglu¹,

Orailoglu²

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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Increasing IC densities necessitate diagnosis methodologies with enhanced defect locating capabilities. Yet the computational effort expended in extracting diagnostic information and the stringent storage requirements constitute major concerns due to the tremendous number of faults in typical ICs. In this paper, we propose an RT-level diagnosis methodology capable of responding to these challenges. In the proposed scheme, diagnostic information is computed on a grouped fault effect basis, enhancing both the storage and the computational aspects. The fault effect grouping criteria are identified based on a module structure analysis, improving the propagation ability of the diagnostic information through RT modules. Experimental results show that the proposed methodology provides superior speed-ups and significant diagnostic information compression at no sacrifice in diagnostic resolution, compared to the existing gate-level diagnosis approaches.

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Invariance-based on-line test for RTL controller-datapath circuits

Cited by 9 publications

References 17 publications

Hierarchical constraint conscious RT-level test generation

Hierarchical constraint conscious RT-level test generation

Non-intrusive design of concurrently self-testable FSMs

Efficient RT-level fault diagnosis methodology

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