Automated synthesis of SEU tolerant architectures from OO descriptions

Abstract

SEU faults are a well-known problem in aerospace environment but recently their relevance grew up also at ground level in commodity applications coupled, in this frame, with strong economic constraints in terms of costs reduction. On the other hand, latest hardware description languages and synthesis tools allow reducing the boundary between software and hardware domains making the high-level descriptions of hardware components very similar to software programs. Moving from these considerations, the present paper analyses the possibility of reusing Software Implemented Hardware Fault Tolerance (SIHFT) techniques, typically exploited in microprocessor based systems, to design SEU tolerant architectures. The main characteristics of SIHFT techniques have been examined as well as how they have to be modified to be compatible with the synthesis flow. A complete environment is provided to automate the design instrumentation using the proposed techniques, and to perform fault injection experiments both at behavioural and gate level. Preliminary results presented in this paper show the effectiveness of the approach in terms of reliability improvement and reduced design effort.

An application specific signal processor for gaseous detector systems in high energy physics experiment.

“…Is also very important to cite the works Bavache et al (2020), Stamenkovic and Petrovic (2016), Oh and Kaneko (2015) and Chiusano, Carlo and Prinetto (2002) addressing automated strategies for fault tolerance in device, circuit, and system. Where Bavache et al (2020) operates over system on chips, Chiusano, Carlo and Prinetto (2002) deals with synthesis in general and Oh and Kaneko (2015) is more directed to data-path creation.…”

“…Is also very important to cite the works Bavache et al (2020), Stamenkovic and Petrovic (2016), Oh and Kaneko (2015) and Chiusano, Carlo and Prinetto (2002) addressing automated strategies for fault tolerance in device, circuit, and system. Where Bavache et al (2020) operates over system on chips, Chiusano, Carlo and Prinetto (2002) deals with synthesis in general and Oh and Kaneko (2015) is more directed to data-path creation. Quijada et al (2019) and Hindman et al (2011) are also important contributions to automation in fault tolerance where logic design methodology for radiation hardened by design high-speed logic using fine-grained triple modular redundancy are presented, which is similar to one of the techniques of protection further used in the present work.…”