A Parallel Processing Hardware Architecture for Elliptic Curve Cryptosystems

Sakiyama, Kazuo; Mulder, Elke De; Preneel, Bart; Verbauwhede, Ingrid

doi:10.1109/icassp.2006.1660801

Cited by 24 publications

(21 citation statements)

References 16 publications

(12 reference statements)

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“…The implementation from [20] is quite fast because of the use of fixed-base comb method. Compared to the state-of-the-art hardware implementations [21,22], software implementations are still slower. However, coprocessors add area and complexity to the whole system, and have far less flexibility than software implementations.…”

Section: Resultsmentioning

confidence: 98%

Elliptic curve cryptography on embedded multicore systems

Fan

Sakiyama

Verbauwhede

2008

Des Autom Embed Syst

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The increasing use of network-connected embedded devices and online transactions creates a growing demand of network security for embedded systems. The security requirements, such as authentication, confidentiality and integrity, always make computationally intensive processes and can easily become the bottleneck of the related applications. In this paper we implement an embedded multicore system, and explore the task scheduling methods in different levels. First, we propose an instruction scheduling method that utilizes all the cores to perform one modular operation in parallel. Second, we perform multiple modular operations with multiple cores in parallel. The performance of those two implementations is compared and a scheduling method combining these two types of parallelism is proposed. We discuss the details of our proposed method by using an FPGA implementation of ECC over a prime field.

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Section: Resultsmentioning

confidence: 98%

Elliptic curve cryptography on embedded multicore systems

Fan

Sakiyama

Verbauwhede

2008

Des Autom Embed Syst

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“…Higher-radix Montgomery multiplier implementations have been reported in [12], [13], [14] (radix-4), [15], [16] (radix-8), [17], [18], [19] (radix-16), [20] (radix-32), [21] (radix-64), and [22] (radix-256). Higher-radix multipliers typically result in faster multiplications, but also require more area than radix-2 multipliers.…”

Section: Introductionmentioning

confidence: 98%

Pipelined modular multiplier supporting multiple standard prime fields

Alrimeih

Rakhmatov

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Computationally-intensive cryptographic applications are critically dependent on the efficiency of modular multiplications. It is desirable for a modular multiplier to offer not only high performance, but also a certain degree of flexibility, supporting multiplications over finite fields of varying size. We propose a fast and flexible modular multiplier over five prime fields GF (p), standardized by NIST for use in elliptic curve cryptography, where the five special primes p are of size 192, 224, 256, 384, and 521 bits. A prime-specific datapath configuration of our multiplier is established automatically, based on an external control word that identifies a NIST prime in use. The pipeline latency of our multiplier (implemented on a Virtex-6 FPGA and running at 100 MHz) is 80 ns for 192-bit, 224-bit, and 256-bit NIST primes, and 200 ns for 384-bit and 521-bit NIST primes. The main limitation of this work is that our multiplier currently supports only the NIST prime fields. We believe that such a limitation is justifiable, as the NIST prime fields are widely used in practice and enable performance improvements through specialized hardware optimizations.

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“…Most of them perform scalar multiplication on Weierstrass curves and target various FPGA platforms. Typical examples-that have a similar security level as Curve25519-are given in [1,14,15,25,26,28,30,35].…”

Section: Introductionmentioning

confidence: 99%

NaCl’s Crypto_box in Hardware

Hutter

Schilling

Schwabe

et al. 2015

Lecture Notes in Computer Science

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Abstract. This paper presents a low-resource hardware implementation of the widely used crypto_box function of the Networking and Cryptography library (NaCl). It supports the X25519 Diffie-Hellman key exchange using Curve25519, the Salsa20 stream cipher, and the Poly1305 message authenticator. Our targeted application is a secure communication between devices in the Internet of Things (IoT) and Internet servers. Such devices are highly resource-constrained and require carefully optimized hardware implementations. We propose the first solution that enables 128-bit-secure public-key authenticated encryption on passivelypowered IoT devices like WISP nodes. From a cryptographic point of view we thus make a first step to turn these devices into fully-fledged participants of Internet communication. Our crypto processor needs a silicon area of 14.6 kGEs and less than 40 µW of power at 1 MHz for a 130 nm low-leakage CMOS process technology.

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A Parallel Processing Hardware Architecture for Elliptic Curve Cryptosystems

Cited by 24 publications

References 16 publications

Elliptic curve cryptography on embedded multicore systems

Elliptic curve cryptography on embedded multicore systems

Pipelined modular multiplier supporting multiple standard prime fields

NaCl’s Crypto_box in Hardware

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