Pipelined modular multiplier supporting multiple standard prime fields

Alrimeih, Hamad; Rakhmatov, Daler

doi:10.1109/asap.2014.6868630

Cited by 10 publications

(5 citation statements)

References 29 publications

(56 reference statements)

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“…Therefore, the comparison of our specific Curve448 design with these designs may not be fair. However, it can be seen from Table 4 that for field sizes of 384 and 521 bits that offer approximately the same security level as Curve448, our design offers faster modular multiplication than all other designs except [34], which has approximately the same performance as our design. However, it utilises a large number of DSP blocks along with the LUTs.…”

Section: Implementation Results and Comparisonmentioning

confidence: 88%

“…A few NIST‐based designs have been proposed for

P - 384

and

P - 521

. The modular multiplier designs in [18, 34] are flexible for all NIST primes, while those presented in [35, 36] target general prime fields. Therefore, the comparison of our specific Curve448 design with these designs may not be fair.…”

Section: Implementation Results and Comparisonmentioning

confidence: 99%

“…The NIST-based algorithms perform a sequence of multi-precision additions and subtractions as an alternative to the costly division. Many design efforts have been made to propose low latency modular multipliers for various ECs meeting different computational time and area requirements [33][34][35][36][37][38][39][40]. However, to the authors' best knowledge only a single design has been proposed for Curve448.…”

Section: Modular Multiplicationmentioning

confidence: 99%

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LUT‐based high‐speed point multiplier for Goldilocks‐Curve448

Shah

Javeed

Shehzad

et al. 2020

IET Computers & Digital Techniques

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Recent studies have shown that existing elliptic curve-based cryptographic standards provide backdoors for manipulation and hence compromise the security. In this regard, two new elliptic curves known as Curve448 and Curve25519 are recently recommended by IETF for transport layer security future generations. Hence, cryptosystems built over these elliptic curves are expected to play a vital role in the near future for secure communications. A high-speed elliptic curve cryptographic processor (ECCP) for the Curve448 is proposed in this study. The area of the ECCP is optimised by performing different modular operations required for the elliptic curve Diffie-Hellman protocol through a unified architecture. The critical path delay of the proposed ECCP is optimised by adopting the redundant-signed-digit technique for arithmetic operations. The segmentation approach is introduced to reduce the required number of clock cycles for the ECCP. The proposed ECCP is developed using look-up-tables (LUTs) only, and hence it can be ported to any field-programmable gate array family or standard ASIC libraries. The authors' ECCP design offers higher speed without any significant area overhead to recent designs reported in the literature.

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Section: Implementation Results and Comparisonmentioning

confidence: 88%

“…A few NIST‐based designs have been proposed for

P - 384

and

P - 521

Section: Implementation Results and Comparisonmentioning

confidence: 99%

Section: Modular Multiplicationmentioning

confidence: 99%

See 1 more Smart Citation

LUT‐based high‐speed point multiplier for Goldilocks‐Curve448

Shah

Javeed

Shehzad

et al. 2020

IET Computers & Digital Techniques

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“…Both of the presented architectures are flexible to perform modular multiplication for any prime number p, Table I shows critical path comparison while Table II [6] and [17] are based on NIST primes and computes 256-bit modular multiplication in 0.08 us and 1.33 us, respectively. Both these design have exploited a special structure of the prime modulus and typically these result in much faster computation time, but lack flexibility.…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…These designs can be classified into three categories: designs based on NIST recommended primes [3], designs based on interleaved multiplication algorithm [4] and designs based on Montgomery multiplication algorithm [5]. A pipelined modular multiplier design reported in [6] can support five NIST recommended primes. Its datapath is comprised of 8 pipeline stages with a latency of 80 ns for prime of sizes 192, 224, 256-bits and 200 ns for 384, 256bits.…”

Section: Introuctionmentioning

confidence: 99%

Serial and parallel interleaved modular multipliers on FPGA platform

Javeed

Wang

Scott³

2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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Modular multiplication is a core operation in all public key based cryptosystems. The performance of these cryptosystems can be enhanced substantially by incorporating an optimized modular multiplier. This paper presents serial and parallel radix-4 modular multipliers based on interleaved multiplication algorithm and Montgomery power laddering technique. A serial radix-4 interleaved modular multiplier provides 50% reduction in the required clock cycles. In addition to the reduction in clock cycles, a parallel modular multiplier maintains a critical path delay comparable to the bit serial interleaved multipliers. The proposed designs are implemented in Verilog HDL and synthesized targeting virtex-6 FPGA platform using Xilinx ISE 14.2 Design suite. The serial radix-4 multiplier computes a 256-bit modular multiplication in 1.3µs, occupies 3.9K LUTs, and runs at 96 MHz. The parallel radix-4 multiplier takes 0.77µs, occupies 5.3K LUTs, and runs at 166 MHz. The results show that the parallel radix-4 modular multiplier provides 62% and 49% speed-up over the corresponding bit serial and bit parallel versions, respectively. Thus, these designs are suitable to accelerate modular multiplication in many cryptographic processors.Index Terms-Finite field, elliptic curve cryptography (ECC), interleaved multiplication, public key cryptography (PKC). I. INTROUCTIONModular multiplication is a tedious operation that is extensively used in a variety of public key cryptographic schemes such as RSA, elliptic curve [1], [2] (ECC). Elliptic curve based cryptographic schemes enjoy much smaller key sizes as compared to RSA, which led to better bandwidth utilization, less storage requirements and lower power consumption. To achieve 128-bit advanced encryption standard (AES) security level, finite field operations in ECC is around 256-bits. Due to its computational complexity, a dedicated hardware implementation is essential to meet timing constraints of many real time applications.For speeding up modular multiplication operation several designs have been presented. These designs can be classified into three categories: designs based on NIST recommended primes [3], designs based on interleaved multiplication algorithm [4] and designs based on Montgomery multiplication algorithm [5]. A pipelined modular multiplier design reported in [6] can support five NIST recommended primes. Its datapath is comprised of 8 pipeline stages with a latency of 80 ns for prime of sizes 192, 224, 256-bits and 200 ns for 384, 256bits. It consumes 8340 slices and 259 dedicated DSPs blocks on Virtex-6 FPGA platform, which may not fit into smaller FPGAs, but is suitable for high speed applications. Designs reported in [7], [8] also exploited special structure of NIST primes. These implementations are devoted to 224 and 256bits and are not able to provide flexibility feature, which may be desirable in many applications.

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