A parallel approach for testing multi-port static random access memories

Abstract

This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling facults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is cornpleted in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells.

Test and diagnosis of word-oriented multiport memories

“…The short defect between word-lines (or between bit-lines) within the same port results in the address decoder fault (AF). The short defect between word-lines (or between bit-lines) of two different ports results in a multiport fault (MPF) [4][5][6]13]. Figure 1 gives a two-port memory example.…”

“…To reduce complexity and be more realistic, we assume that the short defects only occur between adjacent lines, as in previous works [4][5][6]13]. To be more specific, we consider word-line shorts between two different ports in adjacent rows and those in the same row, and bitline shorts between two different ports in adjacent columns and those in the same column.…”

“…In another work, a modified March C test was proposed to cover AND-type and OR-type inter-port faults for a lowpower SRAM with read-only and write-only ports [4]. It has been noted that we can take advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides parallel test access to the ports so that the test length can be reduced [4][5][6]. In [4,5], the target memory was partitioned into several segments, each being tested by different ports simultaneously.…”

“…It has been noted that we can take advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides parallel test access to the ports so that the test length can be reduced [4][5][6]. In [4,5], the target memory was partitioned into several segments, each being tested by different ports simultaneously. In [6], a single-port test algorithm for traditional cell faults with an extended parallel test for port-specific faults was proposed, along with a port scheduling technique for test compaction.…”