Fault simulation and test algorithm generation for random access memories

Wu, Cheng‐Li; Huang, Chih-Tsun; Cheng, Kuo-Liang; Wu, Cheng‐Wen

doi:10.1109/43.992771

Cited by 35 publications

(1 citation statement)

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“…How do we test them by serial interfacing efficiently? Some march tests which use parallel interfacing technique for p-port memories have been proposed in [7] [33], but no research has been done on serial interfacing. This must be investigated and solved as more and more applications do require embedded memories with a large number of ports to enhance the circuit performance.…”

Section: Chaptermentioning

confidence: 99%

A Built-In Self-Testing Method for Embedded Multiport Memory Arrays

Narayanan

Ghosh²,

Jone

et al. 2005

IEEE Trans. Instrum. Meas.

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With recent advances in semiconductor technologies, the design and use of memories for realizing complex system-on-a-chip (SoC) is very widespread. The growing need for storage in computer, communication, and network appliances has motivated new advancements in faster and more efficient ways to test memories. Semiconductor memories are considered to represent 30-35% of the semiconductor market currently. The design flexibility and performance offered by component generators have made the life of the circuit designer easier, but have posted new challenges to test. Thus, as time progresses and the demand for data storage goes high, testing semiconductor memories efficiently becomes more and more important.Efficient testing schemes for single-port memories have been readily available. Multiport memories are widely used in multi-processor systems, telecommunication ASICs etc. Research papers which define multi-port memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multiport memories. In this thesis, we discuss some basics about the architecture of two-port memories and fault models for the same. We will then use the serial testing mechanism to propose new algorithms which can prove effective to reduce the hardware cost considerably in a chip with many multi-port memories. Once we understand how serial interfacing helps testing two-port memories, one possible extension is to use serial interfacing for p-port memories (p>2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead and tolerable test application time. Precise fault modeling and efficient test design are both important to keep the test cost and test time in acceptable limits.I would like to thank the members of my thesis committee, Dr. Carla Purdy and Dr. Harold Carter, for spending their invaluable time reviewing this work. Special thanks are also due to my close friends for the wonderful time I have had in their company. I would like to thank the Almighty for all He has done for me, and pray that He always guides me in the right direction. Last, but not the least, I would like to express my gratitude to my parents who have helped mould me into what I am today.

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Section: Chaptermentioning

confidence: 99%