A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories

Goda, Akira; Moriyama, W.; Hazama, H.; Iizuka, H.; Shimizu, Kazuhiro; Aritome, S.; Shirota, R.

doi:10.1109/iedm.2000.904431

Cited by 4 publications

(3 citation statements)

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“…Since the distance between the CG and the corner region of the active area is shorter in the deep SA-STI case, it is expected that the electric field around the corner region of the active area is enhanced. As the generation of N IT and oxide trapped charges (N OT ) during cycle stress is related to the magnitude of electric field, [20][21][22][23][24][25][26][27][28][29][30][31] lower endurance characteristics are observed in the device with large SA-STI depth.…”

Section: Resultsmentioning

confidence: 99%

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

Yan

Chen

Lee

et al. 2013

Jpn. J. Appl. Phys.

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The program efficiency and endurance characteristics of sub-50 nm NAND flash devices with various self-aligned shallow trench isolation (SA-STI) depths are investigated. Although a large SA-STI depth improves the neighboring floating gate coupling issue and gate coupling ratio, a low program efficiency is also introduced. In addition, lower endurance characteristics are observed in the device with a large SA-STI depth than in the device with a small SA-STI depth. The mechanisms underlying such unfavorable results are discussed on the basis of experimental data and technology computer-aided design simulations.

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Section: Resultsmentioning

confidence: 99%

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

Yan

Chen

Lee

et al. 2013

Jpn. J. Appl. Phys.

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“…However, it is well known that the nitride layer often causes degradation in device reliability due to its high tensile stress. [7][8][9] Recently, there have been many reports in which the dependence of Si-SiO 2 interface trap generation on nitride layer has been investigated using a CPM. [10][11][12] However, there have been no reports yet which show the interface trap characteristics of Si-SiO 2 with various capping materials between the gate stack and an inter layer dielectric (ILD), planarized using CPM in NAND Flash memory.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Si–SiO₂ Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory

Kim¹,

Kim²,

Park³

et al. 2006

jjap

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We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.

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“…Data for the V T shift as a function of the number of reads feature different dependences [255,256], while raw bit-error rate (RBER) data vs. the number of reads reveal a linear dependence whose slope increases with cycles [60,255,257], with a higher BER observed on SLCs than on MLCs. As with SILC, several process optimization [258,259], voltage tuning [255,260] or system-level correction [261] proposals have been put forward to alleviate the issue.…”

Section: Read Disturbmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories

Cited by 4 publications

References 1 publication

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

Analysis of Si–SiO₂ Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

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A novel surface-oxidized barrier-SiN cell technology to improve endurance and read-disturb characteristics for gigabit NAND flash memories

Cited by 4 publications

References 1 publication

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

Characteristics of Sub-50 nm NAND Flash Devices with Various Self-Aligned Shallow Trench Isolation Depths

Analysis of Si–SiO2 Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

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Analysis of Si–SiO₂ Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory