A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations

Abstract

In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the “Y-mode” operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V.

The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

“…However, the increase in disturb, approximately 0.05 V, does not pose significant operational issues. Therefore, the proposed program operation has optimized low-power functionality compared to the conventional FE-NAND operation [19].…”

“…However, the increase in disturb, approximately 0.05 V, does not pose significant operational issues. Therefore, the proposed program operation has optimized lowpower functionality compared to the conventional FE-NAND operation [19]. In Figure 7a,b, a comparison is made between the selected cell and I−V curves of WL 0 and WL 2 under the conditions of BL = 10 V and WL = 7 V, representing Case 1, which corresponds to conventional GIDL program conditions, which were made after program operation was performed in Case 3 under the conditions of BL = 9 V and WL = 5 V.…”

“…Accordingly, research is continuing on 3D FE-NAND flash memory, which adds a ferroelectric thin film to the gate stack of existing NAND flash cells [18]. This study is concerned with the GIDL erase method employed in the CTF structure that was adapted for use in the program operation of FE-NAND flash memory cells [19]. Implementing the GIDL program makes it feasible to perform normal memory operations while maintaining the conventional 3D NAND flash memory structure and wiring method despite the distinctive operational traits of FE-NAND.…”