A novel stability analysis of a PLL for timing recovery in hard disk drives

Gloria, A. De; Grosso, Daniele; Olivieri, Mauro; Restani, G.

doi:10.1109/81.780384

Cited by 11 publications

(9 citation statements)

References 9 publications

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“…Previous studies have been directed at identifying the edge of the stability region of first-order and second-order discrete-time loops in the presence of a loop delay [7], [8]. In practice, it is desirable to operate loops well within the stability region.…”

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confidence: 99%

Effect of loop delay on phase margin of first-order and second-order control loops

Bergmans

2005

IEEE Trans. Circuits Syst. II

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Link to publication Citation for published version (APA):Bergmans, J. W. M. (2005). Effect of loop delay on phase margin of first-order and second-order control loops. IEEE Transactions on Circuits and Systems. II, Analog and Digital Signal Processing, 52(10), 621-625. DOI: 10.1109/TCSII.2005 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract-This paper analyzes the phase margin of first-order and second-order control loops in the presence of a loop delay and establishes rules of thumb on the maximum permissible delay for a given phase margin. Both discrete-time and continuous-time loops are considered. Results are applicable, for example, to adaptive filters and to first-order and second-order phase-locked loops.Index Terms-Adaptive filter, control loop, loop delay, phase margin, phase-locked loop (PLL).

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confidence: 99%

Effect of loop delay on phase margin of first-order and second-order control loops

Bergmans

2005

IEEE Trans. Circuits Syst. II

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“…2) Stability Issues: An important issue that should be considered during timing recovery loop design is the loop stability. It is well known that increasing loop latency results in a rapid reduction of the stable region for the loop filter coefficients and [23], [24]. However, the proposed loop has the additional parameter .…”

Section: B Steady State Jitter and Loop Stabilitymentioning

confidence: 96%

“…Thus, we have (21) For an uncorrelated sequence , the autocorrelation function of is easily shown to be (22) and the PSD is (23) where . For MMSE TED, as seen in (20), and the TED gain to dc noise ratio (TGNR) we are looking for is (24) For the proposed algorithm, focussing on the TED given by (8), we obtain (25) indicating…”

Section: Phase Locked Loop Analysismentioning

confidence: 99%

Timing Recovery in Conjunction With Maximum Likelihood Sequence Detection in the Presence of Intersymbol Interference

Moon

Lee

2008

IEEE Trans. Circuits Syst. I

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A decision-directed timing recovery scheme is discussed that maintains and updates a separate phase estimate path for each survivor data path in the maximum-likelihood (ML) sequence detection of intersymbol interference (ISI) channels. For each survivor path, the phase estimate is updated recursively using symbol-decisions implied in the path. Unlike in the existing per-survivor timing recovery approach, there exists a single global timing loop that operates on a single stream of delayed phase estimate samples released from the merged survivor path or an up-to-date best survivor path. Loop analysis, tracking behavior simulation and BER simulation validate the proposed approach.Index Terms-Timing recovery, synchronization, maximum-likelihood sequence detection, inter-symbol interference (ISI), phase-locked loop, cycle slip.

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“…Bergmans [5] describes the stability regions of high order DPLLs related to changes in the loop gain. De Gloria et al [6] proposes a geometrical and mathematic method to study the stability of loops with a high loop delay for different values of the loop filter coefficients is depicted. None of the previously referenced works offer a simple method to design a loop for a desired lock-up time or loop bandwidth, compensating the undesired effects of loop delays.…”

Section: Introductionmentioning

confidence: 99%

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications

Torres

Perez-Pascual

Sansaloni

et al. 2008

J Sign Process Syst Sign Image Video Technol

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Timing recovery in communication systems with linear modulations is usually performed with a non-dataaided feedback loop based on a fractional interpolator timing corrector and the Gardner's timing error detector. The contribution of this paper is twofold. First, some design rules are given to predict the behaviour of the loop if pipeline is used. Second, it is shown that pipelining can be used to reduce power consumption in a timing feedback loop. A timing recovery loop has been implemented in an FPGA device and power consumption measures indicates that by including 16 extra registers in the loop the power consumption decreases a 63% and the synchronizer can process up to 66.5 MSPS.

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A novel stability analysis of a PLL for timing recovery in hard disk drives

Cited by 11 publications

References 9 publications

Effect of loop delay on phase margin of first-order and second-order control loops

Effect of loop delay on phase margin of first-order and second-order control loops

Timing Recovery in Conjunction With Maximum Likelihood Sequence Detection in the Presence of Intersymbol Interference

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications

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