Abstract:Timing recovery in communication systems with linear modulations is usually performed with a non-dataaided feedback loop based on a fractional interpolator timing corrector and the Gardner's timing error detector. The contribution of this paper is twofold. First, some design rules are given to predict the behaviour of the loop if pipeline is used. Second, it is shown that pipelining can be used to reduce power consumption in a timing feedback loop. A timing recovery loop has been implemented in an FPGA device … Show more
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