A Novel Scan Architecture for Low Power Scan-Based Testing

Abstract

Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.

Physical-aware gating element insertion for thermal-safe scan shift operation

“…Excessive switching activities in scan chains cause a significant power consumption and it results in hotspots which would induce a gate delay increase, scan test failure or even permanent circuit damage. Previous works [1,2,3,4,5,6,7,8,9,10] have proposed that gating elements are added to block transitions originated from the outputs of scan flip-flops through combinational logic thereby reducing the power dissipation. Control-0 and control-1 gating elements are depicted in Fig.…”

A novel X-filling method for capture power reduction

“…The effect of IR drops is particularly problematic at near-threshold voltage condition which decreases the supply voltage to about the threshold voltage for the sake of energy efficiency. Test operations consume more power than normal operations because test patterns make large transitions in circuits under testing [1,2,3]. Timing failures that don't occur in normal operations can be generated by these test operations and these make the overkill problem [4,5].…”