A Novel Methodology To Reduce Leakage Power In Differential Cascode Voltage Switch Logic Circuits

Abstract

Subthreshold leakage current increases exponentially in deep-submicron processes and hence is a crucial factor in scaling down designs. Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, a novel technique that achieves cancellation of leakage effects in both the pull-up transistor (PUT) as well as the pull-down network (PDN) paths of DCVSL circuits is presented. It involves voltage balancing in these paths using sleep transistors. Experimental results show significant leakage power savings (average of 61X at a temperature of 27 o C) in DCVSL circuits employing this sleep circuitry when compared to standard DCVSL circuits. At any given temperature, using our methodology the leakage power loss for DCVSL circuits is constant. A 4.31X improvement (on an average) in leakage savings using our methodology was observed when compared with the traditional power-gating technique.

On Improving the Performance of Dynamic DCVSL Circuits

“…To improve the performance in submicron region, these currents need to be minimized. Various leakage reduction techniques based on the use of sleep transistor [15] and high threshold voltage transistors [16] are available for static DCVSL circuits. These techniques require either routing of sleep signal [15] or a complex algorithm for selection of high threshold voltage transistors.…”

“…Various leakage reduction techniques based on the use of sleep transistor [15] and high threshold voltage transistors [16] are available for static DCVSL circuits. These techniques require either routing of sleep signal [15] or a complex algorithm for selection of high threshold voltage transistors. A selfcontrolled technique named LECTOR [14] is presented for CMOS circuits, which reduces both types of currents and is adapted for dynamic DCVSL circuits, and the resulting topology is referred to as proposed architecture-2 (PA-2).…”

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

“…Differential cascode voltage switch logic (DCVSL) [12] is one of the most well‐known binary logic styles with high‐speed operation and distinctive applications due to its inbuilt redundancy and self error‐checking capability [13, 14]. In addition, this logic style decreases the number of parasitic capacitances on the output interconnection by eliminating the complementary pull‐up network (PUN) [15]. However, static DCVSL (SDCVSL) suffers from high power dissipation more than the traditional CMOS family due to non‐symmetrical PUN and pull‐down network (PDN).…”