Due to the continuous downsizing of MOSFET (Metal Oxide Semi-conductor Field Effect Transistor) devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (Leakage Control Input DEPendent) is proposed for Nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various Short Gate (SG) FinFET logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71 % and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of PVT (Process Voltage and Temperature) variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68 % & 43.93% for PDP metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16nm technology node for FinFET logic devices using PTM model (Multigate BSIM-CMG) on HSPICE tool.