A novel low-latency, high-speed DDFS architecture

Abstract

A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency (requires 11 clock cycles) pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of u 4 1.5 10 . The FPGA implementation of the proposed design has an SFDR of -94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion..

Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA

“…Functional simulation means to simulate the logical function of the designed circuit to test if it can meet the design requirement. Usually the waveform can directly show the relation between the input and the output signal [14].…”

Efficient FPGA Implementation of Direct Digital Frequency Synthesizer for Software Radios

“…Thus, DDFS is a very important part of [3]. The pipelined ROM-less DDFS architecture can also be implemented for high Speed using trigonometric approximation technique for the requirement of frequency upconversion in wireless communication transceiver [4]. The commonly used silicon solutions for SDR implementations are Field Programmable Gate Arrays (FPGA), Digital Signal Processors (DSP), General Purpose Processors (GPP) & Application Specific Integrated Circuits (ASIC).…”