A novel high-speed sense-amplifier-based flip-flop

Strollo, A.G.M.; De, Davide; Napoli, Ettore; Petra, Nicola

doi:10.1109/tvlsi.2005.859586

Cited by 73 publications

(54 citation statements)

References 13 publications

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“…To evaluate the performance of the proposed BBDSAFF, comparison was performed with other high-performance designs, including the conventional SAFF [6], the Nikolic SAFF [7] and the Strollo SAFF [8]. All the flip-flops were implemented using the SMIC 0.18 μm CMOS process.…”

Section: Fig 4 Layout Of Bbdsaffmentioning

confidence: 99%

“…As a result, a SAFF is usually used in memory cores and low-swing bus drivers to improve performance or reduce power dissipation. Several high-performance SAFF structures have been proposed recently [6][7][8], all of which are based on the circuit conventional sense amplifier flip-flop. The one proposed by Matsui et al [6] is characterised by a near-zero setup time, a reduced hold time, a low clock load and true single-phase operation.…”

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Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range

Deng¹,

Mo²

2015

Electron. lett.

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A new boost bulk-driven sense-amplifier-based flip-flop (BBDSAFF) is presented. First, thanks to the boost and bulk-driven technique, the BBDSAFF consumes much lower power and can operate normally in the ultra-wide voltage range. Secondly, the adopted pseudo-PMOS dynamic technique in the RS latch output stage can greatly reduce the delay and improve the driving capability. The simulation results show advantages of high-speed, low power dissipation and very small and symmetrical rise/fall delay. Under the same simulation conditions, power dissipation, delay and PDP of the Strollo sense-amplifier-based flip-flop is 31 μW, 107 ps and 3.32 fJ whereas that of the proposed bulk-driven SAFF is 29 μW, 94 ps and 2.73 fJ. This low power consumption and high-speed BBDSAFF can be applied in various fields, such as ultra-dynamic voltage scaling VLSI, circuits, low power dissipation counter-clock systems and microprocessors.Introduction: With CMOS process downscaling and the operation frequency increasing, power reduction has become an important design issue for circuits and applications. Advance microprocessors are composed of a large number of registers or flip-flops, which consume 27-60% of the total system power [1]. Recently, ultra-dynamic voltage scaling (UDVS) has become the most efficient approach for reducing power consumption [2]. Generally, the optimal supply voltage for a given process and the threshold voltage depends on both logic style and logic functions to be implemented, but the optimal supply voltage for all digital implementations will be significantly lower than the allowed supply voltage for that process. Voltage scaling reduces the active energy and unfortunately the speed as well [3]. So far, the UDVS technology is only applied to combinational logic circuits. All the registers or flipflops in the UDVS systems work at the allowed supply voltage for the process. For UDVS VLSI it is crucial to design a low-power high-speed flip-flop operating in the ultra-wide voltage range.A lot of research has been carried out to improve the performance of flip-flops [4,5]. Gao et al. [4] proposed a novel master-slave D flip-flop and [5] presented a DCVSL flip-flop, both of which are the best candidates for high-speed applications but require a higher supply voltage and have more power dissipation. The sense-amplifier-based flip-flop (SAFF) is the best choice for the ultralow-voltage technique [1]. As a result, a SAFF is usually used in memory cores and low-swing bus drivers to improve performance or reduce power dissipation. Several high-performance SAFF structures have been proposed recently [6-8], all of which are based on the circuit conventional sense amplifier flip-flop. The one proposed by Matsui et al.[6] is characterised by a near-zero setup time, a reduced hold time, a low clock load and true single-phase operation. However, it has asymmetrical delay with a slow high-to-low delay. Although Nikolic et al.'s SAFF [7] has symmetric delay and large driving capability, its power dissipation is not so satisfactory. ...

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Section: Fig 4 Layout Of Bbdsaffmentioning

confidence: 99%

mentioning

confidence: 99%

Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range

Deng¹,

Mo²

2015

Electron. lett.

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“…(SAFF, Fig. 4) [17] is known to be one of the fastest CMOS flip-flops. Fully dynamic power consumption makes it an attractive candidate and a speed of 5.8 Gbps with 10 % safety margin can be achieved.…”

Section: Slvs Output Driver Saff and Ldomentioning

confidence: 99%

A 5.8-Gbps low-noise scalable low-voltage signaling serial link transmitter for MIPI M-PHY in 40-nm CMOS

Nieminen

Tikka

Antonov

et al. 2014

Analog Integr Circ Sig Process

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A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200-400 mV pp signals at date rates of 1.25-5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm 2 , while the actual driver occupies only 190 lm 2 . In this work it was confirmed that a low-power SLVS driver meets the stringent commonmode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below -138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS predrivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44-1.4 mW/Gbps with external clock and 2.6-4.7 mW/Gbps with clock synthesizer.

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“…Moreover, power dissipation was also divided into three components internal power, clock power and data power. Accordingly, power-delay product was considered as the figure of merit (FOM) by most designers and it was extensively used in the literature for comparing the various combinational and sequential circuit designs (Chung et al 2002;Aezinia et al, 2006;Nedovic et al, 2002;Tschanz et al, 2001;Strollo et al, 2005). This paper also addressed the problem of optimising a FF for minimum power-delay product using Levenberg-Marquardt (LM) algorithm embedded in SPICE.…”

Section: Introductionmentioning

confidence: 99%

A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits

Singh¹,

Tiwari²,

Gupta³

2013

IJCAD

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This paper presents a comprehensive comparison between Levenberg-Marquardt (LM) and logical effort (LE) theory-based optimisation techniques. While LM is a classical approach for optimisation and is embedded in SPICE, logical effort-based approach is contemporary, design specific and needs simple back of the envelope calculations for optimisation of digital circuits. Both the approaches have been used by digital circuit designers in the literature for comparing a proposed digital circuit with the existing designs while optimising any given design for timing, power and area parameters. The goal of writing this paper is to make digital system designers gain an insight into the procedures used for optimising digital circuits while at the same time a well-defined approach using LM algorithm is provided that can be easily automated with the current generation CAD tools. For the purpose of comparison some standard circuits were chosen and optimised for minimum PDP and PDAP. SPICE simulations have been extensively used for comparing the two methodologies in a 180 nm\1.8 V CMOS technology.Keywords: VLSI; digital CMOS circuits; logical effort theory; Levenberg-Marquardt algorithm; power-delay product; power-delay-area product.Reference to this paper should be made as follows: Singh, K., Tiwari, S.C. and Gupta, M. (2013) 'A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits', Int.

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A novel high-speed sense-amplifier-based flip-flop

Cited by 73 publications

References 13 publications

Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range

Boost bulk‐driven sense‐amplifier flip‐flop operating in ultra‐wide voltage range

A 5.8-Gbps low-noise scalable low-voltage signaling serial link transmitter for MIPI M-PHY in 40-nm CMOS

A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits

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