A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors

Sethi, Manan; Sharma, K. G.; Dobriyal, Paanshul; Rajput, Navya; Sharma, Geetanjali

doi:10.5120/13393-1035

Cited by 7 publications

(7 citation statements)

References 8 publications

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“…While low V T transistors are used for logic gates present in the circuit to maintain circuit performance. In [11] Forced Stacking technique is proposed where an existing transistor is partitioned into two transistors whose size is half to that of actual transistor. This forms a stack of transistors.…”

Section: Existing Methods For Power Reductonmentioning

confidence: 99%

A novel high performance low power CMOS NOR gate using Voltage Scaling and MTCMOS technique

Handa

Chawla

Sharma

2014

2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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CMOS logic is extensively used in VLSI circuits but due to scaling of technology, the threshold voltage of the transistors used in CMOS circuits decrease which cause an increase in leakage power. Dynamic power consumption, which is proportional to square of supply voltage V DD further adds to the overall power dissipation. This results in low battery life of mobile devices. In this brief, a novel method to curtail both dynamic power dissipation and leakage power is proposed. The proposed method combines Voltage Scaling and Multi-Threshold CMOS (MTCMOS) technique which helps in reducing dynamic and static power dissipation respectively without degrading the circuit's performance. The proposed technique saves power dissipation by 30% to 90% as compared to conventional CMOS and other existing techniques. A 2-input NOR gate is implemented using the proposed VS-MTCMOS technique in sub-threshold region over different temperatures. Tanner EDA Tool is used to simulate the designed circuit.

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Section: Existing Methods For Power Reductonmentioning

confidence: 99%

A novel high performance low power CMOS NOR gate using Voltage Scaling and MTCMOS technique

Handa

Chawla

Sharma

2014

2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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“…Hence it is quickly evaluated to provide the output. The projected logic circuit provides the pliability to style the logic circuit; therefore it will be used to style period domino logic with unvaried circuits [20].…”

Section: Dynamic Logic Static Invertermentioning

confidence: 99%

Performance Analysis of High Speed Domino CMOS Logic Circuits

SinghRathor¹,

Khandelwal²,

Akashe³

2014

IJCA

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As the demand of low power high performance arithmetic circuits multiplies, during this paper, we aim to introduce a style of latest MT-CMOS domino logic and FTL dynamic logic technique to style adder circuit. The MT-MOS transistors cut back the facility dissipation by minimizing sub threshold run current in the introduced domino logic circuits. The MT-NMOS semiconductor connected in discharging path of output electrical converter may be applied for pipeline structure to scale back the facility consumptions and increase fan-out. Dynamic logic vogue CMOS circuit is employed to enhance the speed and cut back the world of style by decreasing the device count. The introduced FTL dynamic logic circuit improves the performance by evaluating the computational blocks partially before its input signals are formalized and then rapidly perform a final evaluation as soon as the inputs arrive. This dynamic logic formation is like minded for an arithmetic circuit wherever the important path s created of an outsized cascade of inverting gates is created.The mixture of MT-CMOS and dynamic logic circuit provides high fan-out, high change frequencies with each lower delay and dynamic power consumption. The simulation results of those projected low power high performance circuits provide 75% power reduction, three times redoubled high speed operation and active space reduction, whereas revealing lower sensitivity to power provide, temperature, electrical phenomenon load and method variations than the dynamic domino CMOS technologies.

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“…Problems with [15][16][17][18] are the growing number of transistors due to stacking effect resulting in large area and delay significantly, but proposed technique uses stacked transistors in very small part of network i.e. LECTOR cell, which is shown in Figure 2(a).…”

Section: Introductionmentioning

confidence: 99%

“…This technique exploits the dependence of I sub on the source terminal voltage. Simultaneous turning off of the two divided transistors induces reverse bias between them [15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

Alimoradi¹,

Rostami²,

Karami³

2018

IJCA

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In this paper, a novel approach at circuit level named LSP is proposed by combination of LECTOR, Stack and Pass transistors techniques to decrease leakage power dissipation during active and standby mode. As a result, pass transistors are utilized to maintain logic state of network in the standby mode. Proposed technique simulation has been performed using HSPICE software in 32 nanometer technology with supply voltage 0.6V. According to achieved results by NAND gate and full adder circuits, sub-threshold current is decreased by 80% in compared to base case, 70% to LECTOR and 20% to Sleepy Keeper.

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A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors

Cited by 7 publications

References 8 publications

A novel high performance low power CMOS NOR gate using Voltage Scaling and MTCMOS technique

A novel high performance low power CMOS NOR gate using Voltage Scaling and MTCMOS technique

Performance Analysis of High Speed Domino CMOS Logic Circuits

Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits

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