CMOS logic is extensively used in VLSI circuits but due to scaling of technology, the threshold voltage of the transistors used in CMOS circuits decrease which cause an increase in leakage power. Dynamic power consumption, which is proportional to square of supply voltage V DD further adds to the overall power dissipation. This results in low battery life of mobile devices. In this brief, a novel method to curtail both dynamic power dissipation and leakage power is proposed. The proposed method combines Voltage Scaling and Multi-Threshold CMOS (MTCMOS) technique which helps in reducing dynamic and static power dissipation respectively without degrading the circuit's performance. The proposed technique saves power dissipation by 30% to 90% as compared to conventional CMOS and other existing techniques. A 2-input NOR gate is implemented using the proposed VS-MTCMOS technique in sub-threshold region over different temperatures. Tanner EDA Tool is used to simulate the designed circuit.
In any integrated circuit power consumption plays a paramount role and is considered as one of the top challenges in International technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in subthreshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forced stack technique. The present technique (VS-STACK) features very low power dissipation as compared to its standard CMOS counterparts in subthreshold region. The power consumption is curtailed by 20% to 90% together with a better power delay product (PDP) over a supply voltage range. The technique is tested on a 2-input NOR gate in the 45nm process. Tanner Tool EDA 13.0v is used for simulation.
The colossal portion of power in CMOS circuits is consumed during switching which is termed as dynamic power consumption. This absorbs more than 60% of the overall power in the circuit. However as the technology scales down, subthreshold leakage becomes commensurable to dynamic power dissipation. This happens as a result of reduction in threshold voltage and device geometry. In this brief, a high performance and power efficient technique is proffered which operates in subthreshold region. The proposed (VS-TG) technique curtails both dynamic and static power dissipation. The dynamic power dissipation is reduced by deploying Voltage Scaling technique while leakage or static power dissipation is lowered with Transistor Gating technique. The total power consumption is reduced by 30% to 90%. The proposed technique is implemented on 2-input NOR gate at different voltages at 10 °C, 20 °C and 30 °C. Tanner Tool EDA at 45nm process is used for simulation.
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