A novel geometry for circular series connected multilevel inductors for CMOS RF integrated circuits

Aguilera, J.; Meléndez, Juan; Berenguer, Roc; Sendra, José Ramón Sendra; Hernández, A.; Pino, J. del

doi:10.1109/ted.2002.1003756

Cited by 7 publications

(4 citation statements)

References 9 publications

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“…By using multilevel inductors instead of the conventional single-level or planar inductors, area minimization can also be accomplished [11][12][13][14][15] (see Figure 2a). In the multilevel structure, the coil is expanded vertically, while in the single level structure, the inductor is implemented using a single metal layer.…”

Section: Area Reduction Techniquesmentioning

confidence: 99%

Area Efficient Dual-Fed CMOS Distributed Power Amplifier

et al. 2018

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In this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing conventional spiral inductors are employed. Additionally, a novel technique based on stacking inductors one on top of others is implemented. Based on these techniques, a 32% area reduction is achieved compared to a conventional design without a noticeable performance degradation. This reduction could be further exploited as the number of stages of the dual-fed DPA increases.

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Section: Area Reduction Techniquesmentioning

confidence: 99%

Area Efficient Dual-Fed CMOS Distributed Power Amplifier

et al. 2018

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“…This permit the user to elongate the spiral in the horizontal or vertical direction. The program also allows to place multilevel spiral inductors, [12], and multiple spirals arranged in the same metal level. Some other features not commented here for simplicity are implemented in our tool.…”

Section: 2mentioning

confidence: 99%

Empirical model of the metal losses in integrated inductors

Pino¹,

Garcı́a²,

González³

et al. 2003

SPIE Proceedings

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Integrated inductors are key components in Radio Frequency Integrated Circuits (RFICs) because they are needed in several building blocks, such as voltage-controlled oscillators, low-noise amplifiers, mixers, or filters. The cost reduction, achieved in the circuit assemblage, makes them preferable to Surface Mounted Devices in spite of the different sources of losses that limits the use of integrated inductors; the substrate losses, and the metal losses. We report, in this work, our research in modeling integrated inductors, particularly the losses in the metals. The model is derived from measurements taken from integrated spiral inductors designed and fabricated in a standard silicon process. The measurements reveal that the widely accepted lumped equivalent model does not properly predict the integrated inductor behavior at frequencies above 3 GHz for our technology. We propose a simple modification in the lumped equivalent circuit model: the introduction of an empirical resistor in the port 1-to-port 2 branch of the equivalent circuit. As a result, it will be demonstrated that the integrated inductor behavior is adequately predicted in a wider frequency range than does the conventional model. In addition, the new model is used to build-up an integrated inductor library containing optimized integrated inductors.

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“…Researchers also aim to integrate MEMS ( inductors [143] There are also some other techniques that are used to enhance the performance of the inductor. The proposed techniques include the use of higher conductivity metal layers, for instance: copper is used to reduce the lossy resistance of the inductor [144] and multi-metal layers are used to increase the effective thickness of the spiral inductor and thereby reduce loss [145][146]. As no special process is required, the technique of multi-layers is widely used.…”

Section: Techniques To Improve the Performance Of The Spiral Inducmentioning

confidence: 99%

“…Here, the designs of circular integrated inductors are our main concerns. It has been reported that circular inductors exhibit better quality factors than square integrated ones at the expense of a slight increase in area [145]. Circular spiral inductors perform 20-30% better than rectangular spiral inductors [147], because rectangular inductors suffer loss caused by scattered currents at the corners.…”

Section: Design Of the Spiral Inductorsmentioning

confidence: 99%

Dual band low-noise amplifier designs for bluetooth and hiperLAN applications

Mou¹

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The last decade saw an explosion of wireless communication technology, together with a rapid development of consumer demand for information. Intensive research efforts have focused on a lot of application areas, such as mobile cellular phones, coreless telephones, global positioning system (GPS), wireless short-distance communication and wireless local area network communication (WLAN/HiperLAN). With so many coexistent communication standards, it is necessary to develop a single-chip transceiver, which can adapt to several bands at the same time. One of the crucial bottlenecks for the multi-standard communications is how to design a low noise amplifier (LNA) that can operate in different frequency bands, as the LNA serves as the first amplification block in the receiving chains. It is also known that, with the scalability of CMOS technology, the obtained cutoff frequency (f T) could be up to one hundred gigahertz. However, the passive on-chip inductors implemented with the current CMOS process are usually lossy and bulky. This is a very significant problem in LNA design, especially in the input stage design using source inductive degeneration architecture. To make the circuit compact and fully integrated, research efforts should be done to reduce the required inductor number and inductor value. Based on the above-mentioned concerns, the investigation on the designs of dual-band LNAs, as well as a modified architecture used for input matching in CMOS LNAs to make the circuit more compact, is presented in this thesis. According to the proposed investigation, a narrow-band LNA (LNA1), a wideband LNA (LNA3) and

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A novel geometry for circular series connected multilevel inductors for CMOS RF integrated circuits

Cited by 7 publications

References 9 publications

Area Efficient Dual-Fed CMOS Distributed Power Amplifier

Area Efficient Dual-Fed CMOS Distributed Power Amplifier

Empirical model of the metal losses in integrated inductors

Dual band low-noise amplifier designs for bluetooth and hiperLAN applications

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