Dual band low-noise amplifier designs for bluetooth and hiperLAN applications

Abstract

The last decade saw an explosion of wireless communication technology, together with a rapid development of consumer demand for information. Intensive research efforts have focused on a lot of application areas, such as mobile cellular phones, coreless telephones, global positioning system (GPS), wireless short-distance communication and wireless local area network communication (WLAN/HiperLAN). With so many coexistent communication standards, it is necessary to develop a single-chip transceiver, which can adapt to several bands at the same time. One of the crucial bottlenecks for the multi-standard communications is how to design a low noise amplifier (LNA) that can operate in different frequency bands, as the LNA serves as the first amplification block in the receiving chains. It is also known that, with the scalability of CMOS technology, the obtained cutoff frequency (f T) could be up to one hundred gigahertz. However, the passive on-chip inductors implemented with the current CMOS process are usually lossy and bulky. This is a very significant problem in LNA design, especially in the input stage design using source inductive degeneration architecture. To make the circuit compact and fully integrated, research efforts should be done to reduce the required inductor number and inductor value. Based on the above-mentioned concerns, the investigation on the designs of dual-band LNAs, as well as a modified architecture used for input matching in CMOS LNAs to make the circuit more compact, is presented in this thesis. According to the proposed investigation, a narrow-band LNA (LNA1), a wideband LNA (LNA3) and