A novel FPGA compliant micropipeline

Zafar, Y.; Ahmed, M. M.

doi:10.1109/tcsii.2005.850778

Cited by 9 publications

(3 citation statements)

References 13 publications

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“…Their focus has been on synchronous digital circuits. There have been some recent efforts to prototype asynchronous circuits on both commercial [14][15][16][17] and academic FPGAs [4,[18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Burst-Mode Asynchronous Controllers on FPGA

Oliveira

Strum

Sato

2008

International Journal of Reconfigurable Computing

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FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

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Section: Introductionmentioning

confidence: 99%

Burst-Mode Asynchronous Controllers on FPGA

Oliveira

Strum

Sato

2008

International Journal of Reconfigurable Computing

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“…The main drawbacks are: the designer should start from a dataflow specification and the granularity of the logic blocks is designed to make them compatible with dataflow constructs. The approach in [8] is based on micropipeline implementations, while the work in [9] presents test results for a highly pipelined asynchronous FPGA. A flexible FPGA that can be targeted to several different design styles is proposed in [10].…”

Section: Introductionmentioning

confidence: 99%

Asynchronous circuit design on reconfigurable devices

Mocho

Sartori

Ribas

et al. 2006

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design

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This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full adders and ripple carry adders, as well as self-timed ring based applications. The comparison analysis has been carried out by prototyping the circuits on standard programmable logic devices, and using the development tools provided by vendors. Although the feasibility of asynchronous circuits has been demonstrated in such devices, the experimental results clearly show the inefficiency of such a kind of digital system implementation. This is mainly due to the architecture characteristics of the programmable devices and the logic synthesis realized by the development environments. Remarks and suggestions are derived from this study for a new FPGA architecture devoted to asynchronous design.

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“…It shows that the symmetric C-Element was the most energyefficient implementation, achieving the same delay as the conventional C-Element using 45% less energy. A similar study is also found in [37], which uses first-order analysis in A very interesting approach to integrate micropipelines into FPGA circuits is presented in [48]. This is done by introducing delay pads that can be customized for each stage o f the micropipeline.…”

Section: Multi-threshold Asynchronous Pipeline Circuitsmentioning

confidence: 90%

Multi-threshold asynchronous pipeline circuits

Shreih¹

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Direction du Patrimoine de I'edition 395, rue W ellington Ottawa ON K1A 0N4 Canada i * i Canada R eproduced with perm ission o f the copyright owner. F urther reproduction prohibited w itho ut perm ission. AbstractPower consumption o f integrated circuits has been rapidly increasing over the past decades, and this is expected to continue for the foreseeable future due to increasing integration and higher frequencies o f operation. High power consumption results in shorter battery life and excessive heat generation, which negatively affects reliability and necessitates the design o f complex cooling systems. Therefore, it is essential to develop techniques for low power design while maintaining high performance.This thesis is focused on using multi-threshold circuit-level techniques that maintain high performance while allowing a reduction in the power supply voltage in order to reduce power consumption. These techniques are applied to asynchronous circuits, including micropipelines and GasP pipelines. The resulting circuits are then simulated and compared. This is the first attempt, as far as we know, that combines multi-threshold and asynchronous circuit techniques. As such, multi-threshold C-Element and GasP circuit structures are proposed to take advantage of multi-threshold voltage techniques to minimize static power dissipation and to maximize performance. Applications o f multi threshold voltage techniques to delay elements and dual edge-triggered flip flops, both o f which are used in asynchronous micropipelines, are also examined. Also, two application circuits are designed including custom layout. The selected application circuits are a micropipeline FIFO and a pipelined GasP 16-bit Brent Kung adder. Post-Layout extracted simulations are then run on these application circuits to prove the concept.ii R eproduced with perm ission o f the copyright owner. F urther reproduction prohibited w itho ut perm ission.The proposed multi-threshold C-Element based pipelines were found to outperform standard micropipelines by achieving higher performance and lower dynamic and static power dissipation. These include new C-Element structures that were designed specifically to take advantage o f multi-threshold techniques. The proposed multi threshold GasP pipeline outperformed standard GasP pipelines as well. It also performed better than the proposed multi-threshold C-Element based pipelines.

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A novel FPGA compliant micropipeline

Cited by 9 publications

References 13 publications

Burst-Mode Asynchronous Controllers on FPGA

Burst-Mode Asynchronous Controllers on FPGA

Asynchronous circuit design on reconfigurable devices

Multi-threshold asynchronous pipeline circuits

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