Burst-Mode Asynchronous Controllers on FPGA

Abstract

FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

“…A GALS system consists of many synchronous functional modules (that may be IPs), which carries its own individual clock signals and communicate to each On the other hand, the ports proposed in [21][22][23] were specified in XBM (Extended Burst-Mode) and BM (Burst-Mode). These ports were implemented, respectively, in 3D [25] and Minimalist [26] tools, on Huffman architecture with output feedback. These ports are controllers of bounded gate and wire delay (BGWD) class, interacting with the environment in the generalized fundamental mode (GFM), leading to a high necessity of timing analysis.…”

An Asynchronous Interface with Robust Control for Globally-Asynchronous Locally-Synchronous Systems

“…and Nowick (1993) proposed the insertion of delay elements on the feedback wires in order to avoid essential hazard in burst-mode controllers. Oliveira et al (2008) proposed a sufficient condition that guarantees essential hazard-free operation on burst-mode controller without the need for extra delay elements, when mapped on VLSI_DSM or any type of LUT-based FPGA. The absence of delay elements is highly desirable when considering FPGA devices (difficulties in implementing this kind of elements) and, furthermore, in aerospace applications, in which the harsh environment must change the behavior of electronic components.…”

“…Figure 7 shows the state flow map of HP-mpfor-pkt. As shown by Oliveira et al (2008), which applies the rule generalized Ungle to check for essential hazard, this states flow map is subjected to essential hazard. The essential hazard depends on the code that the don't-care assumes, when held the logic coverage free of logic hazard.…”

“…The super-state concept will guarantee the latter condition. According to Oliveira et al (2008), the concept of super-state is presented. It is used to obtain an implementation EHF.…”

“…• Use the algorithm of and derive the minimum set of XBM flow charts; • Encode XBM flow tables using the adjacency diagram (Unger, 1969); • For each coded XBM flow table, insert the essential superstates, as seen in the previous section; • Perform the logic minimization, logic-hazard-free, for each "non-input" signal in the "standard RS" and "machine Huffman with output fed back" architectures (Oliveira et al, 2008).…”