A novel erasing technology for 3.3 V flash memory with 64 Mb capacity and beyond

Flash memory cells-an overview

“…Besides the already mentioned method of iterating the erase algorithm, two self-convergent methods have been proposed, both relying on reprogramming techniques after erasure: hot-carrier injection (HCI) reprogramming [64] (i.e., ap- plying 5 V on drain and grounding word-lines for 0.5 s) or FN channel reprogramming [65] (i.e., applying 16 V at the word-lines). The erase scheme proposed in [64] uses channel-electron-induced avalanche HCI to bring the erase distribution to convergence after FN tunneling erase.…”

“…The erase scheme proposed in [65] is a two-step procedure that starts by applying a negative high voltage to the control gate to erase the cell, followed by the application of a positive high voltage to the control gate to inject a few electrons from the substrate back to the FG to reprogram the cell to decrease the erase distribution. This technique is not truly self-convergent, however, since erase distribution spreads after reaching a minimum.…”

Reliability of erasing operation in NOR-Flash memories

“…Limits on reading margins are very important especially for multilevel and scaled technologies using low supply voltages [4]. For example, in a 3.3 V technology the target distribution width should be about 1 V in order to prevent bitline leakage.…”

“…Less dispersion of FN curves is obtained injecting electrons from the more regular and smooth substrate interface (from[4]). …”

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Simply put, as trapped negative oxide charge builds up, it reduces injection, giving a negative V T shift that is balanced by the positive V T shift given by the charge itself. This "converging" behavior of the FN tunneling operation has been in fact exploited to tighten the V T distribution after erase [73].…”