A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

Loubet, N.; Devarajan, Thamarai Selvi; Zhang, J.; Miao, Xin; Sankar, M.; Breton, Mary; Chao, Robin; Greene, Andrew; Yu, Le; Frougier, Julien; Chanemougame, D.; Kal, Subhadeep; Tapily, Kandabara; Smith, Jake; Basker, Veeraraghavan; Mosden, Aelan; Biolsi, Peter; Hurd, Trace; Divakaruni, R.; Haran, Bala; Bu, H.; Alix, Cheryl; Pancharatnam, S.; Zhou, Huimei; Durfee, Curtis; Belyansky, M.; Haller, N.; Watanabe, Kôji

doi:10.1109/iedm19573.2019.8993615

Cited by 59 publications

(55 citation statements)

References 3 publications

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“…Their process flows are equivalent to [16], [17]. Source/drain (S/D) height (H sd ), gate height (H g ), and M0 height (H M0 ) are referred from several TEM images [7], [11]. All the devices have the S/D doping of 2×10 20 cm -3 and the punch through stopper (PTS) doping of 2×10 18 cm -3 to minimize the leakage currents flowing below the gate.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…Meanwhile, Si nanosheet FETs (NSFETs) have been introduced to increase the channel effective widths (W eff ) for greater current drivability under the same footprint while maintaining superior electrostatics through gate-all-around (GAA) structure [6]. In addition, NSFETs can adjust the drain currents (I ds ) by changing the NS width (W NS ), which enables CMOS-compatible layout design [3], [7], [8].…”

Section: Introductionmentioning

confidence: 99%

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Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

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Analog/RF performances of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) were investigated and compared thoroughly using fully-calibrated TCAD. NSFETs have greater current drivability and gate-to-channel controllability than FinFETs under the same footprint, thus achieving larger intrinsic gain. But the cutoff frequencies (F t) of FinFETs and NSFETs are comparable due to larger gate capacitances (C gg) of NSFETs compensating DC performance improvements. Gate resistances (R g) of NSFETs are larger because of their metal gate (MG) configuration surrounding the channels, longer MG height by the topmost NS spacing region, and the bottom transistor, thus degrading maximum oscillation frequency (F max). Device design guidelines of FinFETs and NSFETs are also studied for better intrinsic gain, F t , and F max. Intrinsic gain is improved by better electrostatics, whereas F t increases by greater current drivability over C gg. For larger F max , careful device design is required to compensate between R g , C gg , output resistance, and F t. Overall, NSFETs outperform FinFETs in terms of intrinsic gain, F t , and F max , thus NSFETs are promising for analog/RF applications.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

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“…However, both the above-mentioned approaches to form suspended channels encountered a mechanical instability, known as stiction, which is associated with the capillary force of chemicals during wet-etching [9]. Fortunately, this concern has been avoided by improved dry etching and supercritical drying [10][11][12][13]. The other concern during the suspension of channels is vertical stress associated with gravity.…”

Section: Introductionmentioning

confidence: 99%

Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs

Lee

Park

2021

Electronics

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Mechanical stress is demonstrated in the fabrication process of nanosheet FETs. In particular, unwanted mechanical instability stemming from gravity during channel-release is covered in detail by aid of 3-D simulations. The simulation results show the physical weakness of suspended nanosheets and the impact of nanosheet thickness. Inner spacer engineering based on geometry and elastic property are suggested for better mechanical stability. The formation of wide contact area between inner spacer and nanosheet, as well as applying rigid spacer dielectric material, are preferred.

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“…Taku Iwase is with Research and Development Group, Hitachi, Ltd., Kokubunji, Tokyo 185-8601, Japan (taku.iwase.tu@hitachi.com). isotropic silicon-germanium (SiGe) etching for inner-spacer formation [7][8][9]. A simplified GAA-FET manufacturing flow is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Hirotaka Hamamura is with Research and Development Group, Hitachi, Ltd., Kokubunji, Tokyo 185-8601, Japan (hirotaka.hamamura.nk@hitachi.com). [8]. However, the formation mechanism of rounding has not been clarified, and understanding this mechanism is important for further rounding reduction.…”

Section: Introductionmentioning

confidence: 99%

Formation Mechanism of Rounded SiGe-Etch Front in Isotropic SiGe Plasma Etching for Gate-All-Around FETs

Zhao

Iwase

Satake³

et al. 2021

IEEE J. Electron Devices Soc.

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We investigated the formation mechanism of a rounded silicon-germanium (SiGe)-etch front (rounding) in gateall-around field-effect transistor (GAA-FET) manufacturing. This rounding is created by the isotropic etching of the SiGe layer after anisotropic etching of the SiGe/Si stack, which degrades device characteristics. The etch-time dependence of the rounding amount during isotropic SiGe etching with nitrogen trifluoride plasma indicates that rounding is mainly formed in an initial stage of SiGe etching, namely, etch time less than 15 s. Cross-sectional scanning transmission electron microscopy and energy dispersive x-ray spectroscopy (STEM EDX) measurement indicated that a Ge-containing layer formed on the sidewall of SiGe/Si patterns before isotropic SiGe etching. From these results, we propose a formation model of SiGe rounding below. The Ge composition in the Ge-containing layer has a gradient due to ion-assisted Ge diffusion during anisotropic etching of the SiGe/Si stack. This gradient induces rounding during isotropic SiGe etching because the etch rate of the SiGe layer decreases as the Ge composition decreases. To validate our model, the Gecontaining layer after anisotropic etching was removed by postetch treatment and the Ge spectra on the sidewall was reduced to the detection limit of STEM EDX. As a result, the rounding amount after isotropic SiGe etching improved from 2.7 to 1.8 nm. This reduction indicates that the formation of the Ge-containing layer during anisotropic etching of the SiGe/Si stack is one of the main causes of rounding after isotropic SiGe etching.

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A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

Cited by 59 publications

References 3 publications

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs

Formation Mechanism of Rounded SiGe-Etch Front in Isotropic SiGe Plasma Etching for Gate-All-Around FETs

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