A novel configuration for UWB LNA suitable for low-power and low-voltage applications

Nakhlestani, Amir; Hakimi, Ahmad; Movahhedi, Masoud

doi:10.1016/j.mejo.2012.04.004

Cited by 17 publications

(11 citation statements)

References 19 publications

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“…Comparison mainly focused on noise figure (NF), input reflection coefficient (S 11 ), output reflection coefficient (S 22 ), power gain (S 21 ) and power consumption for 3.1-10.6 GHz UWB frequency. The LNAs implemented in References [8,23,25] uses common-source resistive feedback topology for wideband input matching, but the noise figure was in 3.0-5.3 dB range and consumed more power as compared to the LNA proposed in this paper. A noise cancelling technique was utilized in References [14,23] with a high power consumption of 9.97 mW and 23.23 mW respectively.…”

Section: Simulation Resultsmentioning

confidence: 93%

“…It gives reasons for low-power very-large scale integration (VLSI) design industries and researchers to develop low-power, low-noise, and reliable UWB radio-frequency integrated circuits (RFICs) for these applications. Moreover, continuous shrinking in complementary metal oxide semiconductor (CMOS) chip fabrication technologies and split manufacturing techniques in RF designs [6,7], makes it possible to design and fabricate RFICs on the nanometer scale [8,9].…”

Section: Introductionmentioning

confidence: 99%

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A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

Singh

Arya

Kumar

2018

JLPEA

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An ultra-wideband (UWB) low noise amplifier (LNA) for 3.3–13.0 GHz wireless applications using 90 nm CMOS is proposed in this paper. The proposed LNA uses an improved common-gate (CG) topology utilizing feedback body biasing (FBB), which improves noise figure (NF) by a considerable amount. Parallel-series tuned LC network was used between the common-gate first stage and the cascoded common-source (CS) stage to achieve the maximum signal flow from CG to CS stage. Improved CS topology with a series inductor at the drain terminal in the second stage connected and cascoded CS third stage provides high power gain (S21) and bandwidth enhancement throughout the complete UWB. A common-drain buffer stage at the output provides high output reflection coefficient (S22). It achieves an average power gain (S21) of 14.7 ± 0.5 dB with a noise figure (NF) of 3.0–3.7 dB. It has an input reflection coefficient (S11) less than −11.7 dB for 3.3–13.0 GHz frequency and output reflection coefficient (S22) of less than −10.6 dB with a very high reversion isolation (S12) of less than −72.4 dB. It consumes only 5.2 mW from a 0.7 V power supply.

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Section: Simulation Resultsmentioning

confidence: 93%

Section: Introductionmentioning

confidence: 99%

A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

Singh

Arya

Kumar

2018

JLPEA

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“…One approach to further decrease the power consumption is using lower‐supply voltage. On the other hand, the supply voltage reduces with the continuous shrinking of the transistor dimensions, but one key challenge in bringing out lower‐supply voltage requirements is the threshold voltage (V th ) does not scale down with the supply voltage . This constraint hardens the decrease of the amount of V th lower than its today's available value.…”

Section: Principles Of the Proposed Distributed Amplifier Designmentioning

confidence: 99%

“…Because a reduced supply voltage has a large effect on the power dissipation, to address this need, some of researches have focused on utilizing forward‐body‐bias technique, which reduces the transistors' threshold voltage effectively and leads to utilize lower‐supply voltage . To reduce the supply voltage of the proposed DA and to achieve low‐power consumption, a folded structure and forward body bias have been employed in design of the proposed gain stage .…”

Section: Principles Of the Proposed Distributed Amplifier Designmentioning

confidence: 99%

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

Saadi

Hakimi

2016

Circuit Theory & Apps

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Summary This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.

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“…A threestage performance optimised LNA has been studied in [11], which provides a power gain S 21 of 8 dB, flat NF of 2.9 dB across the ultra-wideband at the cost of increased chip size. In [12][13][14], it has already been mentioned that under low supply voltage (V dd ), the main task in LNA design is to overcome the existing trade-off among gain, NF, linearity, area, and input matching. Thus, it is really a challenging task to address the existing trade-off among these LNA FOMs for the wideband application.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of wideband low‐power LNA for improved RF performance with compact chip area

Pandey

Gawande

Inge

et al. 2018

IET Microwaves, Antennas & Propagation

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Here, a wideband low‐noise amplifier (LNA) based on the two‐stage cascade configuration is presented to improve the radiofrequency (RF) performance. With the common gate (CG) input stage, the proposed LNA provides wideband input matching, while the wideband gain response was achieved using the peaking inductors inserted at the drain terminals of each stage. With a standard 0.18thinmathspaceμm CMOS process, the chip area of the proposed wideband LNA is only 0.116 mm2. However, it consumes a 5.4 mW power from a supply voltage of Vdd=1thinmathspaceV. From the post‐layout simulation results, it achieves maximum power gain S21 of 11.13 dB at 8.5 GHz, input return loss S11 below −9.44 dB, reverse isolation S12 less than −60 dB, and small group delay variation of ±97 ps across 8.5–20 GHz frequency range. Moreover, noise figure (NF) lies in the range of 2.19–3.23 dB, whereas the NF minimum (NnormalFmin) varies in the range of 1.55–2.91 dB for 8.5–20 GHz frequency range. Apart from this, the proposed LNA achieves an IIP3 of 0.96 dBm, when a two‐tone test is performed with a frequency spacing of 50 MHz.

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A novel configuration for UWB LNA suitable for low-power and low-voltage applications

Cited by 17 publications

References 19 publications

A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

A 0.7 V, Ultra-Wideband Common Gate LNA with Feedback Body Bias Topology for Wireless Applications

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

Design and analysis of wideband low‐power LNA for improved RF performance with compact chip area

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