A novel adder cell for ultra low voltage, ultra low power networks in nanoscale VLSI circuits

Karimi, Gholamreza; Sadeghi, Omid

doi:10.1587/elex.8.478

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…We apply the proposed circuits into 4-bit array multiplier which consists of sixteen NANDs, sixteen buffers, six full adders and four half adders as shown in Fig. 12 [30,31,32]. A0 to A3 and B0 to B3 are input signals while P7 to P0 are the outputs.…”

Section: Bit Multipliermentioning

confidence: 99%

Non-floating and low-power adiabatic logic circuit

Han

Takahashi

Sekine

2019

IEICE Electron. Express

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This paper proposes a new adiabatic logic. Adiabatic logic is a good method to reduce power consumption. Several common adiabatic logics suffer from floating output which results in lack in robustness, by using the periodic power supply. At first, we analyze the floating phenomenon of previously proposed 2PC2AL in this paper. The proposed adiabatic logic can prevent the floating of the nodes to add two logic switches between the power supply and charging-discharging transistor. This paper also reports a comparison of energy dissipation between the different adiabatic logics such as, ECRL, 2N2N2P, 2PASCL, 2PC2AL, and the proposed circuit. In the SPICE simulation, the target application is a 4-bit multiplier for IoT products. Through the simulation, the output of the proposed circuit with cascade connection has a stable function.

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Section: Bit Multipliermentioning

confidence: 99%

Non-floating and low-power adiabatic logic circuit

Han

Takahashi

Sekine

2019

IEICE Electron. Express

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“…Every portable product needs arithmetic circuits for processing of advanced DSP algorithms. In all the arithmetic circuits, FA is the critical entity which has an important role in the amount of total power consumption of the entire digital system . Full adder (FA) is used in several long chain arithmetic circuits such as multipliers, division circuits, 32‐bit RCA etc.…”

Section: Introductionmentioning

confidence: 99%

A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

Goyal¹,

Ubhi

Raj

2019

Circuit Theory & Apps

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Summary This paper presents a highly stable, low leakage inexact full adder (FA) which is based on top gate carbon nanotube field effect transistors (TG‐CNTFET) for motion detector applications. Inexact arithmetic circuits are highly accepted in low power multimedia applications. Circuit level metrics, ie, average power, propagation delay, power‐delay product (PDP), and leakage power dissipation as well as application level metric such as peak signal to noise ratio (PSNR) are considered to compare the performance of proposed inexact FA. All the simulations are performed using HSPICE tool with Stanford 32‐nm TG‐CNTFET model. The operating frequency used for simulation is 1‐Ghz with 0.9‐V supply voltage. Proposed inexact FA successfully achieve manifold reduction in leakage power as well as consume 89.2% lesser energy as compared with latest existing inexact FA while having other parameters in acceptable range. Simulations using MATLAB show satisfactory image quality and PSNR value for motion detection applications. The effect of variations in voltage and temperature on leakage power is also presented which confirms stability of the proposed circuit.

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“…CMOS adders are having significant impact [1] on performance of overall system. Most of the advanced DSP algorithms also use addition as a primary operation, so any improvement in performance parameters of FA circuit can improve the whole system [2].…”

Section: Introductionmentioning

confidence: 99%

A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

Goyal¹,

Ubhi

Raj

2018

Mathematical Problems in Engineering

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In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.

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A novel adder cell for ultra low voltage, ultra low power networks in nanoscale VLSI circuits

Cited by 4 publications

References 5 publications

Non-floating and low-power adiabatic logic circuit

Non-floating and low-power adiabatic logic circuit

A low leakage TG‐CNTFET–based inexact full adder for low power image processing applications

A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

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