A novel 0.1 μm MOSFET structure with inverted sidewall and recessed channel

Recessed channels were used in scaled dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to control the severe short-channel effect. The physical operation and device scalability of the DS-SBMOS resulting from the presence of recessed channels and associated gate-corners are elucidated. The coupling of Schottky and gate-corner barriers has a key function in determining the on-off switching and drain current. The gate-corner barriers divide the channel into three regions for protection from the drain penetration field. To prevent resistive degradations in the drive current, an alternative asymmetric recessed channel (ARC) without a source-side gate-corner is proposed to simultaneously optimize both the short-channel effect and drive current in the scaled DS-SBMOS. By employing the proposed ARC architecture, the DS-SBMOS devices can be successfully scaled down, making them promising candidates for next-generation CMOS devices.

Section: Introductionmentioning

confidence: 99%

Operation and scalability of dopant-segregated Schottky barrier MOSFETs with recessed channels

Shih¹,

Hsia²

2013

“…The reasons for the superiority of grooved gate devices over conventional planar devices in suppressing short channel effects, such as the lowering of threshold voltage with shorter channel lengths and improved hot carrier reliability, have been discussed earlier [1][2][3][4][5][6]. The merits of other related device structures, such as recessed channel MOSFETs [7][8][9] and partially raised source/drain (SD) structures [10,11], have also been investigated for channel lengths in the deep submicrometre regime.…”

Section: Introductionmentioning

confidence: 99%

“…Many techniques such as tilted SD implant have been suggested to control the length and doping profile of this region to enhance device performance [16,17]. Furthermore, many of the other non-conventional device structures, such as recessed channel [7][8][9], raised SD [10,11], fully overlapped nitride etch defined (FOND) [18] and gate-drain overlapped device (GOLD) [19] structures, feature a longer gate-to-SD overlap region to aid the suppression of short channel and hot carrier effects. Extrinsic capacitance models, which are based on approximate doping profiles and simplified expressions for accumulated lengths of this region, such as that given in [20], may prove to be too inaccurate for their analysis.…”

Section: Introductionmentioning

confidence: 99%

Parasitic capacitance characteristics of deep submicrometre grooved gate MOSFETs

Sreelal

Lau²,

Samudra

2002

Grooved gate metal-oxide-semiconductor field-effect transistors (MOSFETs) are known to alleviate many of the short channel and hot carrier effects that arise when MOSFET devices are scaled down to very short channel lengths. However, they exhibit much higher parasitic capacitance with stronger bias dependence when compared to conventional planar devices. In this paper, we present a model for gate-to-drain and gate-to-source capacitance characteristics of a deep submicrometre grooved gate MOSFET. Both the intrinsic and extrinsic parts of the capacitance are modelled separately. In particular, the model presents a novel but simple way to account for the accumulation layer formation in the source/drain region of MOSFETs due to the application of the gate voltage. The results are compared with those obtained from a two-dimensional device simulator. The close match between the modelled and simulated data establishes the validity of the model. The model is then used to account for the superiority of capacitance characteristics of planar device structures and to arrive at optimization guidelines for grooved gate devices to match these characteristics.

“…Much effort is currently devoted to facing the difficulties associated with deep sub-micrometre dimensions [2]. The grooved-gate MOSFETs is considered as the most promising device for suppressing short-channel effects and hot-carrier effects [3][4][5], because structures with shallow junctions or even negative junctions can be fabricated without any increase in series resistance. However, there has been no discussion on the influence of structure on the characteristics of grooved-gate MOSFETs, nor which is the optimal structure for grooved-gate MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

The influence of a concave corner on the characteristics of deep-sub-micrometre grooved-gate PMOSFETs

Ren¹,

Hao²

2001

To improve the performance and reliability of grooved gate MOSFETs, the effects of a concave corner on the characteristics of deep sub-micrometre grooved-gate PMOSFETs are studied using the device simulator MEDICI. The results of our study indicate that the concave corner of a recessed gate influences device characteristics strongly. With an increase of the concave corner, the threshold voltage increases, the current driving capability is improved and the hot-carrier effect is decreased.