A new three dimensional IC fabrication technology, stacking thin film DUAL-CMOS layers

Hayashi, Y.; Oyama, Kenichi; Takahashi, Shuji; Wada, S.; Kajiyana, K.; Koh, Risho; Kunio, Takeshi

doi:10.1109/iedm.1991.235336

Cited by 19 publications

(5 citation statements)

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“…1, one implementation of 3-D integration is to use polymer adhesives, such as polyimide or epoxy, to bond wafers at low curing temperatures ranging from 150 to 400°C. [5][6][7] Interwafer vias are then etched through the ILD, the thinned top Si wafer, and the cured polymer layer, with an approximate depth of 20 µm. 7 Furthermore, via filling is made using oxide spacers for insulation, chemical vapor deposited (CVD) TiN for the metal liner, and CVD W for plug formation.…”

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confidence: 99%

Copper Wafer Bonding

Fan

Rahman

Reif

1999

Electrochem. Solid-State Lett.

198

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Silicon wafers, coated with 300 nm evaporated copper, were successfully bonded at 450°C for 30 min with a postbonding anneal in N 2 for 30 min. The postbonding anneal was required for successful bonding, but the annealing temperature did not influence the bond strength from 400 to 620°C. The inclusion of a tantalum diffusion barrier for Cu did not affect the bonding strength or the bonding temperature.Copper metallization, with low electrical resistivity and high electromigration resistance, 1 is rapidly developing into the mainstream interconnect technology. Along with advances in low k dielectrics, these are two practical approaches in reducing interconnect RC delay in integrated circuits. However, new schemes, such as direct three-dimensional integration, have shown promises in significant reduction of interconnect delay and an increase in system performance. 2,3 In exploring the implementation of 3-D integrated circuits, wafer bonding is an attractive technology option.In direct 3-D integration, active device wafers are bonded together, while all active layers are electrically interconnected using high aspect ratio vias. The bonded device wafers are assumed to contain multiple aluminum metal layers and interlevel dielectrics (ILD), thus requiring low-temperature bonding below 450°C to avoid Al degradation. 4 Referring to Fig. 1, one implementation of 3-D integration is to use polymer adhesives, such as polyimide or epoxy, to bond wafers at low curing temperatures ranging from 150 to 400°C. [5][6][7] Interwafer vias are then etched through the ILD, the thinned top Si wafer, and the cured polymer layer, with an approximate depth of 20 µm. 7 Furthermore, via filling is made using oxide spacers for insulation, chemical vapor deposited (CVD) TiN for the metal liner, and CVD W for plug formation.Instead of polymers, one can also use borophosphosilicate glass (BPSG) as the bonding adhesive. 8 However, when using low melting point glasses (450°C or more) for wafer bonding, global planarity of the glass film is needed for good contact between the wafers and to eliminate void formation. Thus, chemical mechanical polishing (CMP) or reflow of the glass is necessary prior to bonding. For both planarization methods, process variations are difficult to control. To alleviate processing issues such as film planarity or complex deeptrench etching procedures, a metal thermocompression bonding method has been proposed. Thin metal films from both wafers will fuse together upon applying compressive force and heat, which provide enough adhesion to bond the wafers together. 9 Figure 2 shows metal (Cu) bumps on both wafers that can serve as electrical contacts between via on the top wafer and Al interconnects on the bottom wafer. These metal bumps also function as small bond pads for wafer bonding. At the same time, dummy metal patterns can be made to increase the surface area for wafer bonding. They can also act as auxiliary structures such as ground planes or heat conduits for the Si active layers. This paper reports on Cu/Ta wafer...

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mentioning

confidence: 99%

Copper Wafer Bonding

Fan

Rahman

Reif

1999

Electrochem. Solid-State Lett.

198

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“…Various kinds of 3D devices or 3D LSIs have been proposed so far [3,4,5,6,7,8,9,10,11,12,13,14,15,16]. The first 3D LSI test chip having three device layers was fabricated using the poly-Si film which is re-crystallized by laser annealing [3].…”

Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

“…The first 3D LSI test chip having three device layers was fabricated using the poly-Si film which is re-crystallized by laser annealing [3]. Another 3D LSI fabrication process using a thinned-wafer transfer method was also proposed where a thinned LSI wafer is bonded to another LSI wafer after the silicon substrate is completely removed except for device areas [5]. However through-Si vias (TSVs) were not used in these 3D test chips.…”

Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

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“…With the initial attempts starting in 1980s, a number of techniques have been developed. Examples of early techniques include the use of polysilicon [4], recrystallization [5], [6], and microbumps [7], [8]. Each of these has its own advantages and disadvantages.…”

Section: Introductionmentioning

confidence: 99%

Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

Kim

Xue

Tiwari

2007

IEEE Electron Device Lett.

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We describe a low-temperature polymer-based 3-D integration technique for wafer-scale transplantation of micrometer thick circuit and device layers onto another host wafer. The maximum temperature of this approach is 340 • C. It incorporates a low-k semiconductor compatible dielectric bonding media, employs tools that are readily available within a fabrication environment, and is very simple to implement. Another unique characteristic of the approach is the simultaneous separation of the transplanting layer from the donor assembly with the bonding to the host assembly. Alignment registration of several micrometers between device layers is demonstrated. Electrical results of 3-D inverter circuit along with demonstration of four-device-layer 3-D integrated stack are presented. Index Terms-Silicon-on-insulator (SOI), system-on-chip integration, 3-D IC, 3-D integration.

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A new three dimensional IC fabrication technology, stacking thin film DUAL-CMOS layers

Cited by 19 publications

References 0 publications

Copper Wafer Bonding

Copper Wafer Bonding

Recent progress in 3D integration technology

Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

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