A new test generation approach for embedded analogue cores in SoC

Stančić, Mladen; Fang, Liquan; Weusthof, Marcel H.H.; Tijink, R.M.W.; Kerkhoff, Hans G.

doi:10.1109/test.2002.1041840

Cited by 4 publications

(4 citation statements)

References 12 publications

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“…In reference [1], also actual measurements have been carried out with regard to slightly different blocks to support the analogue part of the tests.…”

Section: Resultsmentioning

confidence: 99%

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The test search for true mixed-signal cores

Kerkhoff¹

2005

Microelectronics Journal

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“…In reference [1], also actual measurements have been carried out with regard to slightly different blocks to support the analogue part of the tests.…”

Section: Resultsmentioning

confidence: 99%

“…in the case of high-speed ADCs and especially if these cores are embedded, extensive functional testing becomes problematic in technical and economical sense. This can be a result of for instance the limited bandwidth of the test access mechanism (TAM) for the analogue part [1].…”

Section: Introductionmentioning

confidence: 99%

The test search for true mixed-signal cores

Kerkhoff¹

2005

Microelectronics Journal

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“…In the embedded situation, inputs as well as outputs of the filter core are accessible via wrapper cells similar as suggested within IEEE proposed standard P1500 [7] like the DfT circuitry that have been proposed in [8]. An embedded core can be tested by providing test stimuli to the core and observing test responses of the core by using wrapper cells or by propagating signals through preceding and succeeding cores [9]. The considered part of the SoC is presented in Fig.…”

Section: Embedded Situationmentioning

confidence: 99%

Testability-analysis driven test-generation of analogue cores

Stančić

Kerkhoff

2003

Microelectronics Journal

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“…Now the methodology of analogue IP cores is based on fixed CMOS technology, the analogue IP cores do not have reuse and remigration characteristics. Most previously reported embedded analogue IP cores [1][2][3] with low power require improvement of reuse and remigration.…”

Section: Introductionmentioning

confidence: 99%

Embedded CMOS analogue IP core for SOC applications: an experimental case study

Zhu¹,

Yang²,

Sun³

2004

Semicond. Sci. Technol.

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This paper presents an experimental case study of an embedded CMOS analogue IP core for SOC applications. Based on the research and analysis of embedded analogue IP core characteristics and design specification, the embedded voltage reference IP core is implemented by adopting a high speed self-bias amplifier and the sub-threshold characteristics of MOSFETs. The core has the advantages of temperature compensation and width supply source voltage, and the output voltage of reference can be flexibly changed by adjusting the resistor. The IP core was implemented by TSMC 0.35 µm, 0.25 µm and 0.18 µm CMOS technology. The measured results show a temperature coefficient of less than 15 ppm K −1 and power current of less than 5.2 µA. Finally, the design methodology of the embedded CMOS analogue IP core is summarized.

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A new test generation approach for embedded analogue cores in SoC

Cited by 4 publications

References 12 publications

The test search for true mixed-signal cores

The test search for true mixed-signal cores

Testability-analysis driven test-generation of analogue cores

Embedded CMOS analogue IP core for SOC applications: an experimental case study

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