Embedded CMOS analogue IP core for SOC applications: an experimental case study

Abstract

This paper presents an experimental case study of an embedded CMOS analogue IP core for SOC applications. Based on the research and analysis of embedded analogue IP core characteristics and design specification, the embedded voltage reference IP core is implemented by adopting a high speed self-bias amplifier and the sub-threshold characteristics of MOSFETs. The core has the advantages of temperature compensation and width supply source voltage, and the output voltage of reference can be flexibly changed by adjusting the resistor. The IP core was implemented by TSMC 0.35 µm, 0.25 µm and 0.18 µm CMOS technology. The measured results show a temperature coefficient of less than 15 ppm K −1 and power current of less than 5.2 µA. Finally, the design methodology of the embedded CMOS analogue IP core is summarized.