A new technique for measuring threshold voltage distribution in flash EEPROM devices

Himeno, T.; Matsukawa, N.; Hazama, H.; Sakui, Koji; Oshikiri, M.; Masuda, Keisuke; Kanda, K.; Itoh, Y.; Miyamoto, Junichi

doi:10.1109/icmts.1995.513988

Cited by 15 publications

(2 citation statements)

References 3 publications

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“…The floating gate is not attached to any electrodes or power sources and is generally surrounded by an insulation material [ 1 , 2 ]. The operation of the memory cells is dependent upon the charge stored in the floating gate at the threshold voltage to represent information in these memory devices [ 3 , 4 ]. The performance of the memory cells is determined by the programming speed, which is dominated by the speed of the erasing and writing operations [ 1 , 2 ].…”

Section: Introductionmentioning

confidence: 99%

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

et al. 2022

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To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.

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Section: Introductionmentioning

confidence: 99%

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

et al. 2022

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“…This allows maximum flexibility to achieve a complete characterization of the process. To track the (electrical) evolution of a memory array, V T distributions are usually extracted [8]. From a single cell point of view, the V T value is extracted by increasing the gate voltage V cg until the Sense Amplifier switches (i.e., the applied reading current I read flows through the memory transistor).…”

Section: Eeprom Architecturementioning

confidence: 99%

A new experimental method to extract EEPROM tunnel oxide trap density from threshold voltage distributions

Plantier

Aziza

Portal

et al. 2011

Journal of Non-Crystalline Solids

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Quick address detection of anomalous memory cells in a flash memory test structure

Himeno

Hazama

Yaegashi

et al. 1997

IEEE Trans. Semicond. Manufact.

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A new technique for measuring threshold voltage distribution in flash EEPROM devices

Cited by 15 publications

References 3 publications

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

A new experimental method to extract EEPROM tunnel oxide trap density from threshold voltage distributions

Quick address detection of anomalous memory cells in a flash memory test structure

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