A new systolic array for discrete Fourier transform

Hardware Efficient Fast Computation of the Discrete Fourier Transform

“…The design in [3] reduced the number of required multiplications from 4N to 2N + 2, but the number of required additions remains 4N and the I/O cost is as much as that of the design in [1].…”

“…It exhibits much higher computing parallelism and lower computational complexity than the design in [1]. But the computational complexity will be also high, when the input data are complex.…”

“…The algorithms in [1,2] are based on the processing element (PE) with each requiring one complex multiplication-addition (CMAC), which uses 4 real multiplications and 4 real additions. The design in [1] requires N CMAC processors and each processor requires one I/O channel; therefore both its hardware and I/O cost are high. Although the systolic design in [2] can keep I/O cost low, it also requires N CMAC-based PEs to implement an N-length DFT.…”

“…DFT algorithms implemented with systolic arrays have been discussed in detail [1][2][3][4]. The algorithms in [1,2] are based on the processing element (PE) with each requiring one complex multiplication-addition (CMAC), which uses 4 real multiplications and 4 real additions.…”

A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining

“…On the other hand, the DFT-based designs focus on exploiting the regular data flow in the matrix-vector multiplication for pursuing the features of VLSI implementation. The main approaches adopted in the DFT-based designs include the multiplier-based designs [5,7], the read only memory (ROM)-based designs [6,8,9], and the adder-based designs [IO]. These designs have their own advantages in certain DFT applications, but they still have limitations induced by their encapsulated design approaches.…”