Hardware Efficient Fast Computation of the Discrete Fourier Transform

Abstract

In this paper, a new systolic array for prime N-length DFT is first proposed, and then combined with Winograd Fourier Transform algorithm (WFTA) to control the increase of the hardware cost when the transform length is large. The proposed new DFT design is both fast and hardware efficient. Compared with the recently reported DFT design with computational complexity of O(log N), the proposed design saves the average number of required multiplications by 30 to 60% and reduces the average computation time by more than 2 times, when the transform length changes from 16 to 2048.

A reconfigurable systolic array SoC design for multicarrier wireless applications

“…Both the DFT and FIR filers can be configured by means of regular structures consisting of interconnected multiplier-accumulator (MAC) arithmetic units in which the input data is multiplied by either filter coefficients or "twiddle factors" and the generated partial results are then combined. Systolic arrays with dedicated processing elements have been effectively used to implement FIR filters and DFTs [8][9][10][11][12]. A block diagram of the array architecture intended to support FIR filters, DFTs, as well as, complex DSP functions is depicted in Fig.…”