A New Simulation Method for NBTI Analysis in SPICE Environment

Vattikonda, Rakesh; Luo, Yansheng; Gyure, A.; Qi, Xiaoning; Lo, Sam; Shahram, M.; Cao, Yu; Singhal, K.; Toffolon, D.

doi:10.1109/isqed.2007.21

Cited by 12 publications

(1 citation statement)

References 9 publications

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“…[6] demonstrated analytical iterative equations for computation of NBTI impact for arbitrary waveforms. Numerical methods to solve the exact reaction/diffusion (R/D) physics based model of NBTI has been proposed in [7]. Though the above models are accurate, they are inadequate for simulating a gigahertz signal for the duration of chip's lifetime due to the sheer computation complexity.…”

Section: Previous Workmentioning

confidence: 99%

Analysis and optimization of NBTI induced clock skew in gated clock trees

Chakraborty¹,

Ganesan²,

Rajaram³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact on skew of clock trees. This paper demonstrates a mathematical framework to compute the impact of NBTI on gating-enabled clock tree considering their workload dependent temperature variation. Circuit design techniques are proposed to deal with NBTI induced clock skew by achieving balance in NBTI degradation of clock devices. Our technique achieves up-to 70% reduction in clock skew degradation with miniscule (<0.1%) power and area penalty.

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Section: Previous Workmentioning

confidence: 99%

Analysis and optimization of NBTI induced clock skew in gated clock trees

Chakraborty¹,

Ganesan²,

Rajaram³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

Multilevel Reliability Simulation for IC Design

Sutaria

Velamala

Cao

2013

Bias Temperature Instability for Devices and Circuits

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Reliability Study of the 90 nm CMOS Inverter

Hadi¹,

Soin²,

Hatta³

2011

AIP Conference Proceedings

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Experimental study and modeling of the "adiabatic" section of the constrained vapor bubble heat exchanger AIP Conf.Abstract. The effect of the negative bias temperature instability (NBTI) has been studied on the performance of the CMOS inverter using ELDO analog simulator. A simulation study had been conducted on a CMOS inverter using BSIM3V3 model and focused on the PMOS device of the inverter that was simulated with different elevated temperatures in 10 years' time. In this paper, the effects of the temperature variations on the NBTI are studied. The effect on the device parameters such as threshold voltage (V th ) and the circuit performance had been investigated and explained in detail. The simulation results show and increasing in term of term of threshold voltage and also the propagation delay for both before and after stress conditions. Beside, the voltage transfer characteristic (VTC) gives a significant shift when comparing before and after stress condition especially at higher temperature.

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A New Simulation Method for NBTI Analysis in SPICE Environment

Cited by 12 publications

References 9 publications

Analysis and optimization of NBTI induced clock skew in gated clock trees

Analysis and optimization of NBTI induced clock skew in gated clock trees

Multilevel Reliability Simulation for IC Design

Reliability Study of the 90 nm CMOS Inverter

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