A New Series Resistance and Mobility Extraction Method by BSIM Model for Nano-Scale MOSFETs

Abstract

Note that the bulk charge effect for short channel devices and the INTRODUCTION saturation electric field (Esat) effect in the linear region (Vd-2OmV) As MOSFET gate length scales down to nano scale regime, are neglected in the drain current model of Eq. (1). As~~~~~~~~~~~~~Fg MOFEshows thatt anle optiwne Rsd ofnscalet forour parasitic source/drain series resistance (RSd) becomes one of the Fig. 2 shows that an optimized Rt d of febt165Q*,um for our most critical parameters impacting device performance. Many devices is obtained by minimizing the offset between experimental studies have focused on developing an effective Rsd extraction data and model with several iterations. Fig. 3 shows the IDVG methodology. The "Channel-Resistance method" Li] provides a fitting results in the short channel region. If the final R5d value is simethodoleoway. the extractnRSd-Rhweve method" s no provdes a not correct, the drain current ratio of different LG is not correct simple way to extract Rsd; however, this method is no longer either. Once Rsd is uniquely determined, the gate length adequate as pocket implants are introduced into the nano-scale ependency of iliquely may the gate from MOSFET. In this case, pocket profiles overlap in the short channel dependency of mobility (vaeff(LG)) may also be obtained from region, causing higher effective bulk concentration and resulting in intrinsic drain current via Eq. (3). Fig. 4 shows that NMeff tends to a total resistance which does not scale linearly with channel gate degrade in the deep-submicron region for both N/PMOS due to length (LG) [2]. Another famous method called "Shift & Ratio" halo implants Fig. 5 shows that good agreement between the (S&R) also suffers the similar issue because of its basic model and experimental data for a wide range of LG can be assumption that mobility (uteff) does not change with LG [3]. obtainedafterconsideringthegatelengthdependencyofmobility. Actually, pocket implant degrades ,teff in short channel region id (ext) because of higher effective bulk concentration by the halo Id (int) = R (3) overlapping profile [4]. Therefore, the key point for extracting Rsd I -Id (ext) xVd in nano-scale MOSFETs is to take the impacts of LG dependency Fig. 6 provides the Rsd sensitivity with variations on different of ,ueff into account. In .thi wor l-e key parameters, where Rsd iS the most sensitive to LG but this canIn this work, a simplified BSIM-based model has bee be overcome by careful in-line measurement. It is also worth proposed to solve the above issues contributed by halo implants [5]. ntn httevraino tf a ob iie owti %iIn this new methodology, RSd and ,teff can be uniquely extracted in noting that the variation of i eff has to be limited to within ± 500 if ± nano-scale devices. Furthermore, the extracted LG dependency of 40o Rsd variation is the maximum tolerance level. From our ,teff may serve as a good indicator for monitoring the relationship previous extraction work, it is reasonable to pick up LG equal to between geometry and stress parameters. 80-120n...

A Constant-Mobility Method to Enable MOSFET Series-Resistance Extraction

“…R sd approaches a constant and exhibits no dependence on V bs in the sufficiently high E eff region. The inset shows the R sd values extracted from the proposed method in this letter and the method in [14]. A good agreement is achieved.…”

“…2 lists some of the extracted R sd values. Also shown for comparison are those extracted from a considerable number of devices using BSIM simulation [14]. A reasonable agreement is achieved between the two methods.…”

Investigation of Coulomb Mobility in Nanoscale Strained PMOSFETs

“…The information of N a is important for the following extraction of Coulomb mobility. In order to exclude the parasitic source/drain series resistance (R sd ) effect, the BSIM R sd extraction method is adopted [14]. After R sd is obtained, the ideal drain current can be derived from (1)…”

“…It can be seen that the high vertical field mobility is degraded as L EFF shrinks. The abnormal behavior can be explained by halo pile-up, interface states, oxide charges, neutral defects, and remote Coulomb scattering [4], [6], [8], [10], [11], [14], [15]. Fig.…”

Investigation of analogue performance for process-induced-strained PMOSFETs

“…The devices used in this study were fabricated by state-ofthe-art process-induced uniaxial strained-Si technology [13]. The transistor gate length, L gate , ranges from 1 µm to 50 nm.…”