A new series parallel switched multilevel dc-link inverter topology

Ramkumar, S.; Kamaraj, V.; Thamizharasan, S.; Jeevananthan, S.

doi:10.1016/j.ijepes.2011.10.028

Cited by 61 publications

(43 citation statements)

References 19 publications

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“…This is the motivation to focus on developing converter topologies with reduced component counts and suitable modulation strategies [6]- [9]. Depending on the voltage magnitudes of separate dc sources (SDCs), the MLIs are classified into symmetric and asymmetric topologies [10]- [12]. The magnitudes of the SDCs are equal in symmetric topologies while in the asymmetric topologies they are unequal.…”

Section: Introductionmentioning

confidence: 99%

A Level Dependent Source Concoction Multilevel Inverter Topology with a Reduced Number of Power Switches

Jose¹,

Titus²

2016

Journal of Power Electronics

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Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

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Section: Introductionmentioning

confidence: 99%

A Level Dependent Source Concoction Multilevel Inverter Topology with a Reduced Number of Power Switches

Jose¹,

Titus²

2016

Journal of Power Electronics

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“…However, it requires a large number of semiconductor switching devices and gate driver circuits, which reducing the inverter reliability, complexity, cost and also the system efficiency. For low power application the utilization of a large number of switching devices is inadequate, therefore, researchers continue to focus on reducing the component count of multilevel inverter [15][16][17][18][19][20][21][22][23][24][25].…”

Section: Introductionmentioning

confidence: 99%

Reduction of Components in New Family of Diode Clamp Multilevel Inverter Ordeal to Induction Motor

Angamuthu¹,

Thangavelu²,

Kannan³

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper describes the design and implementation of a new diode clamped multilevel inverter for variable frequency drive. The diode clamp multilevel inverter has been widely used for low power, high voltage applications due to its superior performance. However, it has some limitations such as increased number of switching devices and complex PWM control. In this paper, a new topology is proposed. New topology requires only (N-1) switching devices and (N-3) clamping diodes compared to existing topology. A modified APO-PWM control method is used to generate gate pulses for inverter. The proposed inverter topology is coupled with single phase induction motor and its performance is tested by MATLAB simulation. Finally, a prototype model has built and its performance is tested with single phase variable frequency drive.

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“…However, these conventional multilevel inverter topologies are used by employing a larger number of power switches for a higher number of output voltage levels [4]. To rectify this problem, many topologies are presented [5]- [15]. A new asymmetric topology was proposed in [5].…”

Section: Introductionmentioning

confidence: 99%

“…To rectify this problem, many topologies are presented [5]- [15]. A new asymmetric topology was proposed in [5]. In this topology, a power switch with an anti-parallel diode will create an inter-looping current circulation.…”

Section: Introductionmentioning

confidence: 99%

A New Symmetric Multilevel Inverter Topology Using Single and Double Source Sub-Multilevel Inverters

Ramani¹,

Ali²,

Selvam³

2015

Journal of Power Electronics

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In recent years, the multilevel converters have been given more attention due to their modularity, reliability, failure management and multi stepped output waveform with less total harmonic distortion. This paper presents a novel symmetric multilevel inverter topology with reduced switching components to generate a high quality stepped sinusoidal voltage waveform. The series and parallel combinations of switches in the proposed topology reduce the total number of conducting switches in each level of output voltages. In addition, a comparison between the proposed topology with another topology from the literature is presented. To verify the proposed topology, the computer based simulation model is developed using MATLAB/Simulink and experimentally with a prototype model results are then compared.

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A new series parallel switched multilevel dc-link inverter topology

Cited by 61 publications

References 19 publications

A Level Dependent Source Concoction Multilevel Inverter Topology with a Reduced Number of Power Switches

A Level Dependent Source Concoction Multilevel Inverter Topology with a Reduced Number of Power Switches

Reduction of Components in New Family of Diode Clamp Multilevel Inverter Ordeal to Induction Motor

A New Symmetric Multilevel Inverter Topology Using Single and Double Source Sub-Multilevel Inverters

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