A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

Mahabadi, Seyed Ehsan Jamali; Orouji, Ali A.; Keshavarzi, Parviz; Moghadam, Hamid Amini

doi:10.1088/0268-1242/26/9/095005

Cited by 43 publications

(6 citation statements)

References 26 publications

(28 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…According to equations (1), (2) and (14) and boundary condition (3), we can get the potential expression at any point of the device by using the formula…”

Section: ( ) ( )mentioning

confidence: 99%

“…s the most widely used lateral power device, SOI LDMOS devices combine SOI technology, microelectronic technology and power electronics technology [1]. With its unique isolation performance, small leakage, fast speed and low power consumption, it has always occupied a unique advantage in high-performance single-chip power integration technology, and has been rapidly developed in the past decade [2][3]. The new high-speed, high-integration, low-power switching circuit and power amplifier circuits required by various power conversion and energy processing devices are core devices based on SOI LDMOS devices [4].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

Duan

Xing

Dong

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

The unified analytical model is proposed for SOI LDMOS (Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor) based on the electric field modulation in this paper for the first time. The analytical solutions of the surface electric field distributions and potential distributions are derived on the basis of the 2-D Poisson equation. The variation of the buried layer parameters modulates the surface electric field by the electric field modulation effect to optimize the surface electric field distribution of the device. Also, the simulation results obtained through the simulation software ISE are consistent with the expected results of the analytical model. This not only proves the feasibility of the electric field modulation theory, but also shows that the accurate analytical model will be of great guiding significance for designing and optimizing the same LDMOS based on SOI structures.

show abstract

“…According to equations (1), (2) and (14) and boundary condition (3), we can get the potential expression at any point of the device by using the formula…”

Section: ( ) ( )mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

Duan

Xing

Dong

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…The devices are simulated using two-dimensional ATLAS software [10] with SiC material parameters [11][12][13]. In order to achieve more realistic results, several models are activated in simulation, including the 'SRH' model for Shockley-Read-Hall recombination, the 'Print' model for verifying models and material parameters, the 'Conmob' model for standard concentration-dependent mobility, the 'Fldmob' model for parallel electric field-dependent mobility, the 'Fermi Dirac' model for statistics and the 'Impact Selb' model for impact ionization [14]. Figure 2(a) shows the breakdown voltages with respect to the double recessed gate length (L drg ) in the DS-DRG and SS-DRG structures in a fixed double recessed gate thickness (T drg = 0.05 μm) at V GS = −1 V conditions.…”

Section: Device Structurementioning

confidence: 99%

Investigation of the novel attributes in double recessed gate SiC MESFETs at drain side

Orouji

Razavi

Hosseini

et al. 2011

Semicond. Sci. Technol.

Self Cite

View full text Add to dashboard Cite

In this paper, the potential impact of drain side-double recessed gate (DS-DRG) on silicon carbide (SiC)-based metal semiconductor field effect transistors (MESFETs) is studied. We investigate the device performance focusing on breakdown voltage, threshold voltage, drain current and dc output conductance with two-dimensional and two-carrier device simulation. Our simulation results demonstrate that the channel thickness under the gate in the drain side is an important factor in the breakdown voltage. Also, the positive shift in the threshold voltage for the DS-DRG structure is larger in comparison with that for the source side-double recessed gate (SS-DRG) SiC MESFET. The saturated drain current for the DS-DRG structure is larger compared to that for the SS-DRG structure. The maximum dc output conductance in the DS-DRG structure is smaller than that in the SS-DRG structure.

show abstract

“…It means, at the interface of the extended drain and channel, a new electric field peak creates which reduces the main peak at the interface of source-channel. [15][16][17][18][19] So, the carriers in the channel could not obtain the sufficient energy for reaching to the gate oxide. Therefore, the leakage current reduces significantly in the proposed structure.…”

mentioning

confidence: 99%

Improved Device Performance in Nano Scale Transistor: An Extended Drain SOI MOSFET

Mehrad

Zareiee

2016

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

Reducing the size of SOI MOSFET especially in nano regime for applying them in Integrated Circuits is difficult, because of the important problems of Short Channel Effects (SCE). These effects reduce the reliability of the device and it is objective to decrease them. In this paper, the goal is to propose a new structure for SOI MOSFET to improve SCEs. In this case the, the form of drain and channel is changed to obtain more reliable device. In this case, the drain region is extended into the channel improving the performance of the device. The drain has higher doping concentration, which causes better performance. The simulation with two dimensional ATLAS simulator shows that the new structure has better performance than the conventional one in cases of off current, subthreshold slope, threshold voltage, DIBL, maximum electron temperature and drain current which leads to more reliable device.Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been introduced for amplifying or switching the electronic signals. 1 Their good electrical characteristics in nano scale have made them appropriate for integrating circuits in large scale. 2-5 Moreover, they are widely used in digital Complementary Metal Oxide Semiconductor (CMOS) logic. 6 Primary MOSFETs were developed on a silicon body (substrate) which makes some problems. The considerable capacitances between source/drain and substrate, high leakage current, latch up phenomena, and high consumption power, are the problems which are created because of the silicon substrate. 7,8 To overcome them, Silicon On Insulator (SOI) technology is introduced which can reduce these problems effectively. 9 This technology is composed of three layers: a silicon layer at the bottom, an Insulator layer (normally SiO 2 ) in the middle, and a silicon layer as an active region at the top of the structure. The insulator in the middle of the structure has an important role at which the capacitances between source-drain and the insulator are small. The leakage current gets small because of the small conductivity of the insulator. Besides, the consumption power is reduced and the latch up phenomena is approximately omitted. Therefore, SOI MOSFET technology is very useful for growing the electronic industry. 10 However, in nano scale regime, short channel effects such as Drain Induced Barrier lowering (DIBL) and threshold voltage roll-off have serious influences on the performance of devices. 11,12 Many structures have been proposed during last decade for single gate and multi gate structures that can reduce the short channel effects. 13,14 In this paper, a novel structure is proposed which can reduce the short channel effects. The new structure is based on extending the drain region into the channel which is called Extended Drain in the channel region of SOI MOSFET (ED-SOI). So, the drain region becomes larger and the channel region gets smaller. In this case, the carriers, which participate in the current, can pass from a direction with low resistance since the extended drain has...

show abstract

A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

Cited by 43 publications

References 26 publications

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

Investigation of the novel attributes in double recessed gate SiC MESFETs at drain side

Improved Device Performance in Nano Scale Transistor: An Extended Drain SOI MOSFET

Contact Info

Product

Resources

About