Reducing the size of SOI MOSFET especially in nano regime for applying them in Integrated Circuits is difficult, because of the important problems of Short Channel Effects (SCE). These effects reduce the reliability of the device and it is objective to decrease them. In this paper, the goal is to propose a new structure for SOI MOSFET to improve SCEs. In this case the, the form of drain and channel is changed to obtain more reliable device. In this case, the drain region is extended into the channel improving the performance of the device. The drain has higher doping concentration, which causes better performance. The simulation with two dimensional ATLAS simulator shows that the new structure has better performance than the conventional one in cases of off current, subthreshold slope, threshold voltage, DIBL, maximum electron temperature and drain current which leads to more reliable device.Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been introduced for amplifying or switching the electronic signals. 1 Their good electrical characteristics in nano scale have made them appropriate for integrating circuits in large scale. 2-5 Moreover, they are widely used in digital Complementary Metal Oxide Semiconductor (CMOS) logic. 6 Primary MOSFETs were developed on a silicon body (substrate) which makes some problems. The considerable capacitances between source/drain and substrate, high leakage current, latch up phenomena, and high consumption power, are the problems which are created because of the silicon substrate. 7,8 To overcome them, Silicon On Insulator (SOI) technology is introduced which can reduce these problems effectively. 9 This technology is composed of three layers: a silicon layer at the bottom, an Insulator layer (normally SiO 2 ) in the middle, and a silicon layer as an active region at the top of the structure. The insulator in the middle of the structure has an important role at which the capacitances between source-drain and the insulator are small. The leakage current gets small because of the small conductivity of the insulator. Besides, the consumption power is reduced and the latch up phenomena is approximately omitted. Therefore, SOI MOSFET technology is very useful for growing the electronic industry. 10 However, in nano scale regime, short channel effects such as Drain Induced Barrier lowering (DIBL) and threshold voltage roll-off have serious influences on the performance of devices. 11,12 Many structures have been proposed during last decade for single gate and multi gate structures that can reduce the short channel effects. 13,14 In this paper, a novel structure is proposed which can reduce the short channel effects. The new structure is based on extending the drain region into the channel which is called Extended Drain in the channel region of SOI MOSFET (ED-SOI). So, the drain region becomes larger and the channel region gets smaller. In this case, the carriers, which participate in the current, can pass from a direction with low resistance since the extended drain has...
